Skip to main content
SpringerLink
Log in

Reconfigurable Filter Coprocessor Architecture for DSP Applications

  • Published:
Journal of VLSI signal processing systems for signal, image and video technology Aims and scope Submit manuscript

Abstract

Digital Signal Processing (DSP) is widely used in high-performance media processing and communication systems. In majority of these applications, critical DSP functions are realized as embedded cores to meet the low-power budget and high computational complexity. Usually these cores are ASICs that cannot be easily retargeted for other similar applications that share certain commonalities. This stretches the design cycle that affects time-to-market constraints. In this paper, we present a reconfigurable high-performance low-power filter coprocessor architecture for DSP applications. The coprocessor architecture, apart from having the performance and power advantage of its ASIC counterpart, can be reconfigured to support a wide variety of filtering computations. Since filtering computations abound in DSP applications, the implementation of this coprocessor architecture can serve as an important embedded hardware IP.

This is a preview of subscription content, log in via an institution to check access.

Access this article

Log in via an institution

Price excludes VAT (USA)
Tax calculation will be finalised during checkout.

Instant access to the full article PDF.

Institutional subscriptions

Similar content being viewed by others

References

  1. MPEG-1 and MPEG-2 Standards from ISO, http://www.mpeg.org/MPEG; H.320 Standard from ITU, http://www.itu.int/itudoc/itu-t/rec/h/h320.html.

  2. M. Mouly and M.B. Pantet, “The GSM System for Mobile Communications, Published by Authors, 4 rue Elise e Reclus, F-91120 PALAISEAU, FRANCE, 1993.

  3. Audio & Electroacoustics Technical Committee, “The Past, Present and Future of Audio Signal Processing,” IEEE Signal Processing Magazine, September 1997, pp. 30–57.

  4. P.G. Paulin, C. Liem, T.C. May, and S. Sutarwala, “DSP Design Requirements for Embedded Systems: A Telecommunications Industrial Perspective,” Journal of VLSI Signal Processing, January 1995, vol. 9, pp. 23–47.

    Article  Google Scholar 

  5. B.S. Atal, V. Cuperman, and A. Gersho (Eds.), Speech and Audio Coding for Wireless and Network Applications, Norwell, MA: Kluwer Academic Publishers, 1993.

    Google Scholar 

  6. T.H. Meng, A.C. Hung, E.K. Tsern, and B.M. Gordon, “Low-Power Signal Processing System Design for Wireless Applications,” IEEE Personal Communications, June 1998, pp. 20–31.

  7. E. Biglieri, G. Caire, and G. Taricco, “Coding and Modulation Under Power Constraint,” IEEE Personal Communications, June 1998, pp. 32–39.

  8. B.G. Haskell, P.G. Howard, Y.A. LeCun, A. Puri, J. Ostermann, M.R. Civanlar, L. Rabiner, L. Bottou, and P. Haffner, “Image and Video Coding–Emerging Standards and Beyond,” IEEE Trans. on Circuits and Systems for Video Technology, vol. 8, no.7, November 1998, pp. 814–837.

    Article  Google Scholar 

  9. K. Azadet and C.J. Nicole, “Low-Power Equalizer Architectures for High-Speed Modems,” IEEE Communications Magazine, October 1998, pp. 118–126.

  10. R. Amirtharajah and A.P. Chandrakasan, “Self-Powered Low Power Signal Processing,” IEEE Symposium on VLSI Circuits Digest of Technical Papers, 1997, pp. 25–26.

  11. N.R. Shanbhag and M. Goel, “Low-Power Adaptive Filter Architectures and Their Application to 51.84Mb./sATM-LAN,” IEEE Trans. Signal Processing, vol. 45, no.5, May 1997, pp. 1276–1290.

    Article  Google Scholar 

  12. C. Nicol, P. Larsson, K. Azadet, and J.H. O'Niell, “A Low-Power 128-Tap Digital Adaptive Equalizer for Broadband Modems,” IEEE Jl. of Solid-State Circuits, vol. 32, no.11, November 1997, pp. 1777–1789.

    Article  Google Scholar 

  13. R. Rambaldi, A. Uguzzoni, and R. Guerrieri, “A 35 μ W 1.1 V Gate Array 8 x 8 IDCT Processor for Video Telephony,” IEEE ICASSP, 1998, pp. 2993–2996.

  14. T. Xanthopoulos and A.P. Chandrakasan, “A Low-Power IDCT Macrocell for MPEG-2 MPML Exploiting Data Distribution Properties for Minimal Activity,” IEEE Jl. of Solid-State Circuits, vol. 34, no.5, May 1999, pp. 693–703.

    Article  Google Scholar 

  15. L.E. Thon, “A 480 MHz 11 mWPR4 Viterbi Decoder and Margin Circuit in 0.25 µm CMOS,” IEEE Symposium on VLSI Circuits Digest of Technical Papers, 1998, pp. 148–151.

  16. Motorola DSP Processor, 56300 Series, http://www.motorola.com/SPS/DSP/products/DSP56311.html.

  17. K. Vissers, Invited Session 3.2.1: The TriMedia CPU64 VLIW Media Processor, IEEE ICCD, 1999.

  18. V. Bhaskaran and K. Konstantinides, Image and Video Compression Standards: Algorithms and Architectures, Norell, MA: Kluwer Academic Publishers, 1996.

    MATH  Google Scholar 

  19. MAJC Microprocessor, SUN Microsystems, http://www.sun.com/microelectronics/MAJC.

  20. Pentium II Microprocessor with MMX, Intel Corporation, http://www.intel.com/pentiumII/specs/mmx.html.

  21. MIPS64 Microprocessor, MIPS Technologies, http://www.mips.com/products/s2p2.html.

  22. PowerPC Microprocessor, Motorola & IBM joint effort, http://www.mot.com/SPS/PowerPC.

  23. ARM10 Thumb Microprocessor, ARM, http://www.arm.com/ProCPeripherals/Cores/ARM10.

  24. G.S. Sohi, S. Breach, and T.N. Vijaykumar, “Multiscalar Processors,” 22th IEEE International Symposium on Computer Architecture ISCA-22, 1995.

  25. Multiscalar Processors, http://www.cs.wisc.edu/mscalar.

  26. J. Hennesey and D.A. Patterson, Computer Architecture: A Quantitative Approach, 2nd ed., San Mateo, CA: Morgan Kaufmann, 1996.

    Google Scholar 

  27. P. Ranganathan, S. Adve, and N.P. Jouppi, “Performance of Image and Video Processing with General-Purpose Processors and Media ISA Extensions,” Proc. 26th International Symposium on Computer Architecture, 1999.

  28. Intel's IA-64 Processor, http://www.software.external.hp.com/software/HPsoftware/IA64/arch.html.

  29. R. Simar, Jr., “Codevelopment of the TMS320C6x VelociTI Architecture and Compiler,” IEEE ICASSP, 1998, pp. 3145–3148.

  30. TMS320C6x DSP Processor, Texas Instruments, www.ti.com/sc/docs/products/dsp/c6000/index.htm.

  31. SC140 DSP Processor, Motorola & Lucent, motorola.com/SPS/DSP/publicity/sc140pr.html.

  32. TM1000 Media Processor, Philips, http://www-us.semiconductors.com/trimedia.

  33. ZSP16401 DSP Processor, ZSP Corporation, http://www.zsp.com/Press/09.14.98/0914-english.html.

  34. P. Faraboschi, G. Desoli, and J.A. Fisher, “The Latest Word in Digital and Media Processing,” IEEE Signal Processing Magazine, March 1998, pp. 59–84.

  35. N. Seshan, “High VelociTI Processing,” IEEE Signal Processing Magazine, March 1998, pp. 86–101.

  36. S. Purcell, “The Impact of Mpact 2,” IEEE Signal Processing Magazine, March 1998, pp. 102–107.

  37. D. Martin and R.E. Owen, “A RISC Architecture with Uncompromised Digital Signal Processing and Microcontroller Operation,” IEEE ICASSP, 1998, pp. 3097–3100.

  38. F. Sijstermans, E.J. Pol, B. Riemens, K. Vissers, S. Rathnam, and G. Slavenburg, “Design Space Exploration for Future TriMedia CPUs,” IEEE ICASSP, 1998, pp. 3137–3140.

  39. P.G. Paulin, C. Liem, M. Cornero, F. Nacabal, and G. Goossens, “Embedded Software in Real-Time Signal Processing Systems: Application and Architecture Trends,” Proc. IEEE, vol. 85, no.3, March 1997, pp. 419–435.

    Article  Google Scholar 

  40. G. Goossens, J.V. Praet, D. Lanneer, W. Geurts, A. Kifli, C. Liem, and P.G. Paulin, “Embedded Software in Real-Time Signal Processing Systems: Design Technologies,” Proc. IEEE, vol. 85, no.3, March 1997, pp. 436–454.

    Article  Google Scholar 

  41. K. Moerman, P. Kievits, E. Lambers, and R. Woudsma, “REAL DSP: Reconfigurable Embedded DSP Architecture for Low-Power/Low-Cost Applications,” Proc. ICSPAT, September 1998, pp. 814–818.

  42. L. Raffo, S.P. Sabatini, M. Mantelli, A.D. Gloria, and G.M. Bisio, “Design of an ASIP Architecture for Low-Level Visual Elaborations,” IEEE Trans. VLSI Systems, vol. 5, no.1, March 1997, pp. 145–153.

    Article  Google Scholar 

  43. MPEG-4 Standard from ISO, http://www.mpeg.org/MPEG.

  44. Home Audio/Visual Interoperability Standard, http://www.havi.org/home.html.

  45. Very high-rate Digital Subscriber Line, http://www.vdsl.org.

  46. H.324 Standard from ITU, http://www.itu.int/itudoc/itu-t/rec/h/h324.html.

  47. A. Kalavade and P.A. Subrahmanyam, “Hardware/Sofware Partioning for Multifunction Systems,” IEEE Trans. CAD of Integrated Circuits and Systems, vol. 17, no.9, September 1998, pp. 819–837.

    Article  Google Scholar 

  48. Universal Mobile Telecommunication Systems (UMTS), 3rd Generation Telecommunication Standard, http://www.umts-forum.org.

  49. K. Ishida, “Technology Innovations in Mobile Computing,” IEEE Symposium on VLSI Circuits Digest of Technical Papers, 1997, pp. 47–50.

  50. A. Bellaouar and M.I. Elmasry, “Low-Power Digital VLSI Design: Circuits and Systems,” Norell MA: Kluwer Academic Publishers, 1996.

    Google Scholar 

  51. S. Santhanam, A.J. Baum, D. Bertucci, M. Braganza, K. Broch, T. Broch, J. Burnette, E. Chang, K.-T. Chui, D. Dobberpuhl, P. Donahue, J. Grodstein, I. Kim, D. Murray, M. Pearce, A. Silveria, D. Souydalay, A. Spink, R. Stepanian, A. Varadharajan, V. von Kaenel and R. Wen, “A Low-Cost, 300 MHz, RISC CPU with Attached Media Processor,” IEEE Jl. of Solid-State Circuits, vol. 33, no.11, November 1998, pp. 1829–1839.

    Article  Google Scholar 

  52. Y. He, I. Ahmad, and M.L. Liou, “A Software-Based MPEG-4 Video Encoder Using Parallel Processing,” IEEE Trans. Circuits and Systems for Video Technology, vol. 8, no.7, November 1998, pp. 909–920.

    Article  Google Scholar 

  53. H. Igura, Y. Naito, K. Kazama, I. Kuroda, M. Motomura, and M. Yamshina, “An 800-MOPS, 100-mW, 1.5-V, Parallel DSP for Mobile Multimedia Processing,” IEEE Jl. of Solid-State Circuits, vol. 33, no.11, November 1998, pp. 1820–1828.

    Article  Google Scholar 

  54. J.A.J. Leijten, J.L. van Meerbergen, A.H. Timmer, and J.A.G. Jess, “PROPHID:AHeterogenous Multi-Processor Architecture for Multimedia,” IEEE ICCD, 1997, pp. 164–169.

  55. O. Fatemi and S. Panchanathan, “Fractal Engine: An Affine Video Processor Core for Multimedia Applications,” IEEE Trans. Circuits and Systems for video Technology, vol. 8, no.7, November 1998, pp. 892–908.

    Article  Google Scholar 

  56. S. Ramanathan, V. Visvanathan, and S.K. Nandy, “A Computational Engine for Multirate FIR Digital Filtering,” Signal Processing, vol. 79, no.2, December 1999, pp. 213–222.

    Article  MATH  Google Scholar 

  57. A.V. Oppenheim and R.W. Schafer, “Discrete-Time Signal Processing,” Englewood Cliffs, NJ: Prentice-Hall, 1989.

    MATH  Google Scholar 

  58. P.P. Vaidyanathan, “Multirate Systems and Filter Banks,” Englewood Cliffs, NJ: Prentice-Hall, 1993.

    MATH  Google Scholar 

  59. S.-S. Ahn and P.J. Voltz, “Convergence of the DLMS Algorithm with Decreasing Step Size,” IEEE ICASSP, 1997, pp. 1854–1857.

  60. S.-S. Ahn and P.J. Voltz, “Convergence of the Delayed Normalized LMS Algorithm with Decreasing Step Size,” IEEE Trans. Signal Processing, vol. 44, no.12, December 1996, pp. 3008–3016.

    Article  Google Scholar 

  61. K.K. Parhi, C.-Y.Wang, and A.P. Brown, “Synthesis of Control Circuits in Folded Pipelined DSP Architectures,” IEEE J. Solid-State Circuits, vol. 27, no.1, January 1992, pp. 29–43.

    Article  Google Scholar 

  62. T.C. Denk and K.K. Parhi, “Synthesis of Folded Architectures for Multirate DSP Algorithms,” IEEE Trans. VLSI Systems, vol. 6, no.4, December 1998, pp. 595–607.

    Article  Google Scholar 

  63. S. Ramanathan and V. Visvanathan, “Low-Power Configurable Processor Array for DLMS Adaptive Filtering,” Proc. 10th Intl. Conf. VLSI Design, Piscataway, NJ: IEEE Press, January 1997, pp. 198–203.

    Chapter  Google Scholar 

  64. V.V. Kaenel, P. Macken, and M.G.R. Degrauwe, “A Voltage Reduction Technique for Battery-Operated Systems,” IEEE J. Solid-State Circuits, vol. 25, no.5, October 1990, pp. 1136–1140.

    Article  Google Scholar 

  65. V. Gutnik and A.P. Chandrakasan, “Embedded Power Supply for Low-Power DSP,” IEEE Trans. VLSI Systems, vol. 5, no.4, December 1997, pp. 425–435.

    Article  Google Scholar 

  66. K.K. Parhi, “High-Level Algorithm and Architecture Transformations for DSP Synthesis,” J. VLSI Signal Processing, vol. 9, no.1, January 1995, pp. 121–143.

    Article  MathSciNet  Google Scholar 

  67. J. Rabaey, L. Guera, and R. Mehra, “Design Guidance in the Power Dimension,” Proc. IEEE ICASSP, 1995, pp. 2837–2840.

  68. M.B. Srivastava, A.P. Chandrakasan, and R.W. Broderson, “Predictive System Shutdown and Other Architectural Techniques for Energy Efficient Programmable Computation,” IEEE Trans. VLSI Systems, vol. 4, no.1, March 1996, pp. 42–55.

    Article  Google Scholar 

  69. T.C. Denk, C.J. Nicol, P. Larsson, and K. Azadet, “Reconfigurable Hardware for Efficient Implementation of Programmable FIR Filters,” IEEE ICASSP, 1998, pp. 3005–3008.

  70. O. Gay-Bellile and E. Dujardin, “Architecture of a Programmable FIR Filter Coprocessor,” IEEE ISCAS, 1998, pp. 433–436.

  71. E. Dujardin and O. Gay-Bellile, “Software Implementation of a ADSL Application with a Convolution Coprocessor,” IEEE ICASSP, 1998, pp. 3053–3056.

  72. R. Jain, P.T. Yang, and T. Yoshino, “FIRGEN: A Computer-Aided Design System for High Performance FIR Filter Integrated Circuits,” IEEE Trans. Signal Processing, vol. 39, no.7, July 1991, pp. 1655–1668.

    Article  MATH  Google Scholar 

  73. S. Balakrishnan and S.K. Nandy, “Arbitrary Precision Arithmetic–SIMD Style,” Proc. 11th Intl. Conf. VLSI Design, Piscataway, NJ: IEEE Press, January 1998.

    Google Scholar 

  74. M. Takahashi, M. Hamada, T. Nishikawa, H. Arakida, T. Fujita, F. Hatori, S. Mita, K. Suzuki, A. Chiba, T. Terazawa, F. Sano, Y. Watanabe, K. Usami, M. Igarashi, T. Ishikawa, M. Kanuzawa, T. Kuroda, and T. Furuyama, “A 60-mW MPEG4 Video Codec Using Clustered Voltage Scaling with Variable Supply-Voltage Scheme,” IEEE Jl. Solid-State Circuits, vol. 33, no.11, November 1998, pp. 1772–1780.

    Article  Google Scholar 

  75. S. Santhanam et al., “A Low-Cost, 300-MHz, RISC CPU with Attached Media Processor,” IEEE Jl. Solid-State Circuits, vol. 33, no.11, November 1998, pp. 1829–1839.

    Article  Google Scholar 

  76. L. Bolcioni, M. Borgatti, M. Felici, R. Rambaldi, and R. Guerrieri, “A Low-Power, Voice-Controlled, H.263 Video Decoder for Portable Applications,” IEEE Jl. Solid-State Circuits, vol. 33, no.11, November 1998, pp. 1810–1819.

    Article  MATH  Google Scholar 

  77. J.A.J. Leijten, J.L. van Meerbegen, A.H. Timmer, and J.A.G. Jess, “PROPHID:AHeterogenous Multi-Processor Architecture for Multimedia,” IEEE ICCD, 1997, pp. 164–169.

  78. V. Visvanathan and S. Ramanathan, “Synthesis of Energy-Efficient Configurable Processor Array,” 1st Intl. Workshop on Parallel Processing, Bangalore, India, Tata McGraw-Hill, December 1994, pp. 627–632.

    Google Scholar 

  79. S.Y. Kung, VLSI Array Processors, Englewood Cliffs, NJ: Prentice-Hall, 1988.

    Google Scholar 

  80. S. Ramanathan and V. Visvanathan, “Low-Power PipelinedLMS Adaptive Filter Architectures with Minimal Adaptation Delay,” Integration, The VLSI Journal, vol. 27, no.1, January 1999, pp. 1–32.

    Article  MATH  Google Scholar 

  81. S. Ramanathan, V. Visvanathan, and S.K. Nandy, “Architectural Synthesis of Low-Power Computational Engines for Subband Adaptive Filtering,” Jl. VLSI Signal Processing, vol. 22, no.3, September 1999, pp. 173–195.

    Article  Google Scholar 

  82. B. Widrow and S.D. Sterns, Adaptive Signal Processing, Englewood Cliffs, NJ: Prentice-Hall, 1985.

    MATH  Google Scholar 

  83. T. Sakurai and A.R. Newton, “Delay Analysis of Series-Connected MOSFET Circuits,” IEEE J. Solid-State Circuits, vol. 26, 1991, pp. 122–131.

    Article  Google Scholar 

  84. U. Ko, P.T. Balsara, and W. Lee, “Low-Power Design Techniques for High-PerformanceCMOSAdders,” IEEE Trans. VLSI Systems, vol. 3, no.2, 1995, pp. 327–333.

    Article  Google Scholar 

  85. S. Ramanathan, V. Visvanathan, and S.K. Nandy, “Synthesis of Configurable Architectures for DSP Algorithms,” Proc. 12th Intl. Conf. VLSI Design, Piscataway, NJ: IEEE Press, January 1999, pp. 350–357.

    Google Scholar 

  86. S. Ramanathan, V. Visvanathan, and S.K. Nandy, “Synthesis of ASIPs for DSP Algorithms,”Integration, the VLSI Journal, vol. 28, no.1, September 1999, pp. 13–32.

    Article  Google Scholar 

  87. M. Potkonjak, M.B. Srivastava, and A.P. Chandrakasan, “Multiple Constant Multiplications: Efficient and Versatile Framework and Algorithms for Exploring Common Subexpression Elimination,” IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, vol. 15, no.2, February 1996, pp. 151–165.

    Article  Google Scholar 

  88. R. Adams and T. Kwan, “A Stereo Asynchronous Digital Sample-Rate Converter for Digital Audio,” IEEE Jl. of Solid-State Circuits, vol. 29, no.4, April 1994, pp. 481–488.

    Article  Google Scholar 

Download references

Author information

Authors and Affiliations

  1. Supercomputer Education and Research Centre, Indian Institute of Science, Bangalore, 560 012, India

    S. Ramanathan, S.K. Nandy & V. Visvanathan

Authors
  1. S. Ramanathan
    View author publications

    You can also search for this author in PubMed Google Scholar

  2. S.K. Nandy
    View author publications

    You can also search for this author in PubMed Google Scholar

  3. V. Visvanathan
    View author publications

    You can also search for this author in PubMed Google Scholar

Rights and permissions

Reprints and permissions

About this article

Cite this article

Ramanathan, S., Nandy, S. & Visvanathan, V. Reconfigurable Filter Coprocessor Architecture for DSP Applications. The Journal of VLSI Signal Processing-Systems for Signal, Image, and Video Technology 26, 333–359 (2000). https://doi.org/10.1023/A:1026555400883

Download citation

  • Published:

  • Issue Date:

  • DOI: https://doi.org/10.1023/A:1026555400883

Search

Navigation