Abstract
The purpose of this paper is to introduce a new I DDQ measurement technique based on active successive approximations, called ASA-I DDQ. This technique has unique features facilitating a speed-up in I DDQ measurement. Experimental results suggest that a significant speed-up factor (up to 4) can be obtained over the QuiC-Mon technique. Such a speed-up is a key element in the replacement of single-threshold I DDQ testing since it amplifies the effectiveness of post-processing techniques.
Similar content being viewed by others
References
R. Aitken, “Diagnosis of Leakage Faults with IDDQ,” Journal of Electronic Testing: Theory and Applications, vol. 3, no. 3, pp. 367-375, 1992.
E.I. Cole Jr. et al., “Transient Power Supply Voltage Analysis for Detecting IC Defects,” in IEEE Int. Test Conf., 1997, pp. 23–31.
W.R. Daasch, J. McNames, D. Bockelman, K. Cota, and R. Madge, “Variance Reduction UsingWafer Patterns IDDQ Data,” in IEEE Int. Test Conf., 2000, pp. 189-198.
A. Gattiker and W. Maly, “Current Signatures,” in IEEE VLSI Test Symp., 1999, pp. 112-117.
C.F. Hawkins and J.M. Soden, “Deep SubmicronCMOSCurrent IC Testing: Is There a Future?,” IEEE Design & Test, vol. 16, no. 4, pp. 14-15, 1999.
S. Jandhyala et al., “Clustering Based Techniques for IDDQ Testing,” in IEEE Int. Test Conf., 1999, pp. 730-737.
B. Krusemen, P. Janssen, and V. Zieren, “Transient Current Testing of 0.25 µmCMOS Devices”, in IEEE Int. Test Conf., 1999, pp. 47-56.
P. Maxwell et al., “Current Ratios: A Self-Scaling Implementation of Current Signatures for Production IDDQ Testing,” in IEEE Int. Test Conf., 1999, pp. 738-746.
A.C. Miller, “IDDQ Testing in Deep Submicron Integrated Circuits,” in IEEE Int. Test Conf., 1999, pp. 724-729.
P. Nigh, W. Needham, K. Butler, P. Maxwell, and R. Aitken, “An Experimental Study Comparing the Relative Effectiveness of Functional, Scan, Iddq, and Delay-Fault Testing,” in IEEE VLSI Test Symp., 1997, pp. 459-463.
Y. Okuda,“DECOUPLE: Defect Current Detection in Deep Submicron IDDQ,” in IEEE Int. Test Conf., 2000, pp. 199-206.
A.V. Oppenheim and R.W. Schafer, Digital Signal Processing, Prentice-Hall, 1975.
E. Peterson and W. Jiang, “Practical Application of Energy Consumption RatioTest,” in IEEE Int. Test Conf., 2001, pp. 386-394.
J.F. Plusquellic, D.M. Chiarulli, and S.P. Levitan, “Digital Integrated Circuit Testing Using Transient Signal Analysis,” in IEEE Int. Test Conf., 1996, pp. 481-490.
R. Rajsuman, “Iddq Testing for CMOS VLSI”, Proc. of IEEE, vol. 88, no. 4, pp. 544-566, 2000.
M. Sachdev, V. Zieren, and P. Janssen, “Defect Detection with Transient Current Testing and its Potential for Deep Sub-micron ICs”, in IEEE Int. Test Conf, 1998, pp. 204-213.
A. Singh, C. Patel, S. Liao, J.F. Plusquellic, and A. Gattiker, “Detecting Delay Faults Using Power Supply Transient Signal Analysis,” in IEEE Int. Test Conf., 2001, pp. 395-404.
C. Thibeault, “An Histogram Based Procedure for Current Testing of Active Defects,” in IEEE Int. Test Conf., 1999, pp. 714–723.
C. Thibeault, “On the Comparison of Δ IDDQ and IDDQ Testing,” in IEEE VLSI Test Symp., 1999, pp. 143-150.
C. Thibeault, “Improving Delta-IDDQ Based-Test Methods,” in IEEE Int. Test Conf., 2000, pp. 207-216.
C. Thibeault, “V DDQ IC Testing System and Method,” US Patent Pending.
P.N. Varyiam, “Increasing the IDDQ Test Resolution Using Current Prediction,” in IEEE Int. Test Conf., 2000, pp. 217-224.
B. Vinnakota, W. Jiang, and D. Sun, “Process-Tolerant Test with the Energy Consumption Ratio,” in IEEE Int. Test Conf., 1998, pp. 1027-1036.
K.M. Wallquist, A.W. Righter, and C.F. Hawkins, “A General Purpose IDDQ Measurement Circuit,” in IEEE Int. Test Conf., 1993, pp. 642-651.
N.H.E. Weste and K. Eshraghian, Principles of CMOS VLSI Design, 2nd ed., Addison-Wesley, 1993.
T. Williams, R. Dennard, R. Kapur, M, Mercer, and W. Maly, “Iddq Test: Sensitivity Analysis of Scaling,” in IEEE Int. Test Conf., 1996, pp. 786-792.