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Enhanced Symbolic Simulation for Functional Verification of Embedded Array Systems

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Abstract

Symbolic simulation is an effective approach for verifying individual array blocks. This paper presents two methods to enhance the capacity of symbolic simulation for handling large and complex embedded array systems. The first method combines an ATPG decision procedure with symbolic simulation. By developing a scheme that enables the ATPG to work effectively with a symbolic simulator, the run-time OBDD sizes can be limited. In the second method, we propose a “dual-rail” symbolic simulator where a given design is partitioned implicitly into control and datapath domains. Symbolic simulation is carried out simultaneously on both domains. We demonstrate and compare the effectiveness of both methods based on verification of the Memory Management Unit (MMU) in Motorola high-performance microprocessors.

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Authors and Affiliations

  1. Department of Electrical and Computer Engineering, University of California, Santa Barbara, CA, USA

    Li-C Wang, Tao Feng & Kwang-Ting (Tim) Cheng

  2. ASP Advanced Tools and Methodologies, Motorola Inc., Austin, TX, USA

    Magdy S. Abadir

  3. Verplex Systems, Inc., Milpitas, CA, USA

    Manish Pandey

Authors
  1. Li-C Wang
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  2. Tao Feng
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  3. Kwang-Ting (Tim) Cheng
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  4. Magdy S. Abadir
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  5. Manish Pandey
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Wang, LC., Feng, T., Cheng, KT.(. et al. Enhanced Symbolic Simulation for Functional Verification of Embedded Array Systems. Design Automation for Embedded Systems 8, 173–188 (2003). https://doi.org/10.1023/B:DAEM.0000003961.86651.2b

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  • DOI: https://doi.org/10.1023/B:DAEM.0000003961.86651.2b

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