Abstract
Complex functionality of today embedded hardware/software systems is principally due to the ability of design teams to select and integrate intellectual property (IP) cores. Their correct integration and the final design testability are a major concern for any design flow. This paper proposes a Web-CAD methodology for IP-core analysis and test based on a client/server architecture. The SystemC language is exploited to define a design verification framework for integration test of IP-cores. Intellectual property of cores is guaranteed by allowing functional test generation on faulty IP-core models without disclosing their internal structure. The methodology can be applied to mixed descriptions based on VHDL and SystemC and remote simulation can be also performed locally to avoid bandwidth bottleneck. Moreover, the same test generation process can be indifferently applied at the functional level or at lower abstraction levels such as RT and gate.
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Fin, A., Fummi, F. A Remote Methodology for Embedded Systems Design and Validation. Design Automation for Embedded Systems 8, 229–247 (2003). https://doi.org/10.1023/B:DAEM.0000003964.80057.ac
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DOI: https://doi.org/10.1023/B:DAEM.0000003964.80057.ac