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A Low-Cost At-Speed BIST Architecture for Embedded Processor and SRAM Cores

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Abstract

We have introduced a low-cost at-speed BIST architecture that enables conventional microprocessors and DSP cores to test their functional blocks and embedded SRAMs in system-on-a-chip architectures using their existing hardware and software resources. To accommodate our proposed new test methodology, minor modifications should be applied to base processor within its test phase. That is, we modify the controller to interpret some of the instructions differently only within the initial test mode. In this paper, we have proposed a fuctional self-test methodology that is deterministic in nature. In our proposed architecture, a self test program called BIST Program is stored in an embedded ROM as a vehicle for applying tests. We first start with testing processor core using our proposed architedture. Once the testing of the processor core is completed, this core is used to test the embedded SRAMs. A test algorithm which utilizes a mixture of existing memory testing techniques and covers all important memory faults is presented in this paper. The proposed memory test algorithm covers 100% of the faults under the fault model plus a data retention test. The hardware overhead in the proposed architecture is shown to be negligible. This architecture is implemented on UTS-DSP (University of Tehran and Iran Communicaton Industries (SAMA)) IC which has been designed in VLSI Circuits and Systems Laboratory.

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Authors and Affiliations

  1. Center for Integrated Circuits & Systems, Department of EE, The University of Texas at Dallas, Richardson, TX, 75083, USA

    M.H. Tehranipour

  2. VLSI Circuits & Systems Laboratory, Department of ECE, The University of Tehran, Tehran, 14399, Iran

    S.M. Fakhraie, Z. Navabi & M.R. Movahedin

Authors
  1. M.H. Tehranipour
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  2. S.M. Fakhraie
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  3. Z. Navabi
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  4. M.R. Movahedin
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Tehranipour, M., Fakhraie, S., Navabi, Z. et al. A Low-Cost At-Speed BIST Architecture for Embedded Processor and SRAM Cores. Journal of Electronic Testing 20, 155–168 (2004). https://doi.org/10.1023/B:JETT.0000023679.08518.bf

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