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Scan Latch Design for Test Applications

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Abstract

This JETTA letter describes a new single-latch scan design that uses a single clock for both scan and functional operations. A test mode signal differentiates between normal and test operations. This new design enjoys savings in circuits, pins, test time, and also enjoys the benefits of a high-speed scan capability.

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References

  1. H. Ando, “Testing VLSI with Random Access Scan,” in Proc. COMPCON, Feb. 1980, pp. 50-52.

  2. P.H. Bardell, W.H. McAnney, and J. Savir, Built-In Test for VLSI: Pseudorandom Techniques, New York: Wiley Interscience, 1987.

    Google Scholar 

  3. P.S. Bottorf, R.E. France, N.H. Garges, and E.J. Orosz, “Test Generation for Large Logic Networks,” in Proc. Design Automation Conf., June 1977, pp. 479-485.

  4. E.B. Eichelberger and T.W. Williams, “A Logic Design Structure for LSI Testability,” J. Design Automation and Fault-Tolerant Computing, vol. 2, pp. 165-178, 1978.

    Google Scholar 

  5. S. Funatsu, N. Wakatsuki, and T. Arima, “Test Generation Systems in Japan,” in Proc. Design Automation Conf., June 1975, pp. 114-122.

  6. C. Hunter, J. Slaton, J. Eno, R. Jessani, and C. Dietz, “PowerPC 603**(TM) Microprocessor: An Array Built-in Self Test,” in Proc. Int. Test Conf., 1994, pp. 388-394.

  7. J. Savir, “Reduced Latch Count Shift Registers,” J. of Elec. Testing, vol. 11, no. 2, pp. 183-185, 1997.

    Google Scholar 

  8. J. Savir, “Scan Latch Design for Delay Test,” in Proc. Int. Test Conf., Nov. 1997, pp. 446-453.

  9. J. Savir, “Distributed Generation ofWeighted Random Patterns,” IEEE Trans. Computers, vol. 48, no. 12, pp. 1364-1368, 1999.

    Google Scholar 

  10. J.H. Stewart, “Future Testing of Large LSI Circuit Cards,” in Proc. Semic. Test Symp., Oct. 1977, pp. 6-15.

  11. J.H. Stewart, “Application of Scan/Set for Error Detection and Diagnostics,” in Proc. Semic. Test Symp., Oct.-Nov. 1978, pp. 152-158.

  12. R. Tekumalla and P.R. Menon, “Delay Testing with Clock Control: An Alternative to Enhanced Scan,” in Proc. Int. Test Conf., Nov. 1997, pp. 454-462.

  13. J.T. Yen, M. Sullivan, C. Montemayor, W. Pete, and R. Evers, “Overview of PowerPC 620 Multiprocessor Verification Strategy,” in Proc. Int. Test Conf., Oct. 1995, pp. 167-174.

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Authors and Affiliations

  1. Department of Electrical and Computer Engineering, New Jersey Institute of Technology, Newark, NJ, 07102, USA

    Amit M. Sheth & Jacob Savir

Authors
  1. Amit M. Sheth
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  2. Jacob Savir
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Sheth, A.M., Savir, J. Scan Latch Design for Test Applications. Journal of Electronic Testing 20, 213–216 (2004). https://doi.org/10.1023/B:JETT.0000023683.62501.ed

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  • DOI: https://doi.org/10.1023/B:JETT.0000023683.62501.ed

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