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Code Generation for Functional Validation of Pipelined Microprocessors

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Abstract

Functional validation of pipelined microprocessors is a challenging task, as the behavior of a pipeline is determined by a sequence of instructions and by the interaction between their operands. This paper describes an approach to automatic test-program generation based on an evolutionary algorithm. The proposed methodology is able to tackle complex pipelined designs. Human intervention is limited to the formalized listing of the instruction set, and also internal parameters of the test program generator are auto-adapted. A prototype was built and exploited to generate test programs for the DLX/pII, a pipelined microprocessor. For the purpose of these experiments, test programs were devised trying to maximize the RT-level statement coverage. However, the method can be used to generate test programs on different target metrics. Results show the feasibility and effectiveness of the method.

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Authors and Affiliations

  1. Dipartimento di Automatica e Informatica, Politecnico di Torino, Torino, Italy

    F. Corno, E. Sanchez, M. Sonza Reorda & G. Squillero

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  1. F. Corno
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  2. E. Sanchez
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  3. M. Sonza Reorda
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  4. G. Squillero
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Corno, F., Sanchez, E., Reorda, M.S. et al. Code Generation for Functional Validation of Pipelined Microprocessors. Journal of Electronic Testing 20, 269–278 (2004). https://doi.org/10.1023/B:JETT.0000029460.80721.4d

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  • DOI: https://doi.org/10.1023/B:JETT.0000029460.80721.4d

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