Skip to main content
SpringerLink
Log in

Distributed Diagnosis of Interconnections in SoC and MCM Designs

  • Published:
Journal of Electronic Testing Aims and scope Submit manuscript

Abstract

An interconnect test and diagnostic scheme based on distributed BIST resources in SOC and MCM designs is described. Test and diagnosis is enabled by embedding cascaded test pattern generators and reconfigurable signature analyzers into the design. The theory of partitioning of linear registers is applied to devise a two phase distributed diagnosis strategy. The design of a novel MISR reconfiguration scheme that enables high diagnosis resolution is presented.

This is a preview of subscription content, log in via an institution to check access.

Access this article

Log in via an institution

Price excludes VAT (USA)
Tax calculation will be finalised during checkout.

Instant access to the full article PDF.

Institutional subscriptions

Similar content being viewed by others

References

  1. P. Bardell, W. McAnney, and J. Savir, Built-In Test for VLSI: Pseudorandom Techniques, New York: John Wiley & Sons, 1987.

    Google Scholar 

  2. D.K. Bhavsar, “Concatenable Polydividers: Bit-Sliced LFSR IC's for Board Self-Test,” in Proc. of International Test Conference, 1985, pp. 88-93.

  3. H. Chang and J. Abraham, “Delay Test Techniques for Boundary Scan Based Architectures,” in Proc. of International Test Conference, 1986, pp. 263-273.

  4. C. Chang and C. Su, “An Universal BIST Methodology for Interconnects,” in Proc. of International Test Conference, 1993, pp. 1615-1618.

  5. C.-A. Chen and S.K. Gupta, “BIST/DFT for Performance Testing of Bare Dies and MCMs,” Proc. of Electro '94, 1994, pp. 803-812.

  6. C.-A. Chen and S.K. Gupta, “Design of Efficient BIST Test Pattern Generators for Delay Testing,” Proc. of IEEE Transactions 306 Pendurkar, Chatterjee and Zorian on CAD of Integrated Circuits and Systems, vol. 15, no. 12, pp. 1568-1575, 1996.

    Google Scholar 

  7. A. Frisch, “Use of Embedded At Speed Test for KGD,” Tektronix EAST Technology Internal Report, 1996.

  8. A. Flint, “Multichip Module Self-Test Provides Means to Test at Speed,” EE-Evaluation Engineering, Sept. 1995, pp. 46-55.

  9. K. Furuya and E.J. McCluskey, “Two Pattern Test Capabilities of Autonomous TPG Circuits,” in Proc. of International Test Conference, 1991, pp. 704-711.

  10. P. Gillis and F. Woytowich, “Delay Test of Chip I/Os Using LSSD Boundary Scan,” in Proc. of the International Test Conference, 1998, pp. 83-90.

  11. S.K. Gupta and C.-A. Chen, “BIST TPGs for Faults in Board Level Interconnect via Boundary Scan,” Proc. of VLSI Test Symposium, 1997, pp. 376-382.

  12. A. Hassan, V. Agarwal, B. Nadeau-Dostie, and J. Rajski, “BIST of PCB Interconnects Using Boundary-Scan Architecture,” IEEE Trans. on Computer Aided Design, vol. 11, no. 10, pp. 1278-1287, 1992.

    Google Scholar 

  13. J. Hagge and R. Wagner, “High Yield Assembly of Multichip Modules Through Known-Good ICs and Effective Test Strategies,” Proc. of the IEEE, vol. 80, no. 12, pp. 1965-1994, 1992.

    Google Scholar 

  14. N. Haider and N. Kanopoulas, “The Split Boundary Scan Register Technique for Testing Board Interconnects,” Proc. of VLSI Test Symposium, 1992, pp. 43-48.

  15. International Semiconductor Technology Roadmap Committee, “International Technology Roadmap for Semiconductors,” 2001.

  16. N. Jarwala, “Designing 'Dual Personality' IEEE 1149.1 Compliant Multi-Chip Modules,” in Proc. of International Test Conference, 1994, pp. 446-455.

  17. N. Jarwala and C. Yau, “Achieving Board-Level BIST Using the Boundary-Scan Master,” in Proc. of International Test Conference, 1991, pp. 649-658.

  18. J. Koeter and S. Sparks, “Interconnect Testing Using BIST Embedded in IEEE 1149.1 Designs,” in Proc. of International ASIC Conference & Exhibition, 1991, pp. P11-2.1-P11-2.4.

  19. E. Kontopidi and J. Muzio, “The Partitioning of Linear Registers for Testing Applications,” Microelectronics Journal, vol. 24, pp. 533-546, 1993.

    Google Scholar 

  20. A. Krasniewski and S. Pilarski, “Circular Self-Test Path: A Low-Cost BIST Technique for VLSI Circuits,” IEEE Trans. Computer-Aided Design, vol. 8, no. 1, pp. 46-55, 1989.

    Google Scholar 

  21. W. McAnney and J. Savir, “There Is Information in Faulty Signatures,” in Proc. of International Test Conference, 1987, pp. 630-636.

  22. I. Parulkar, T. Ziaja, R. Pendurkar, A. D'Souza, and A. Majumdar, “A Scalable, Low Cost Designfor-Testability Architecture for UltraSPARC Chip Multi-Processors,” in Proc. of International Test Conference, 2002, pp. 726-735.

  23. R. Pendurkar, “CA-BIST For Testing Instruction Length Decoder Chip,” Internal Report, Strategic CAD Lab, Intel Corporation, 1997.

  24. R. Pendurkar, A. Chatterjee, and Y. Zorian, “A Distributed BIST Technique for Diagnosis of MCM Interconnections,” in Proc. of International Test Conference, Oct. 1998, pp. 214-221.

  25. R. Pendurkar, A. Chatterjee, and Y. Zorian, “Switching Activity Generation with Automated BIST Synthesis for Performance Testing of Interconnects,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 20, no. 9, pp. 1143-1158, 2001.

    Google Scholar 

  26. R. Pendurkar, A. Chatterjee, and Y. Zorian, “Synthesis of BIST Hardware for Performance Testing of MCM Interconnects,” in Proc. of International Conference on Computer-Aided Design, Nov. 1998, pp. 69-73.

  27. S. Pilarski and A. Pierzynska, “BIST and Delay Fault Detection,” in Proc. of Custom Integrated Circuits Conference, 1992, pp. 13.2.1-13.2.4.

  28. J. Savir andW. McAnney, “Random Pattern Testability of Delay Faults,” in Proc. of International Test Conference, Sept. 1986, pp. 263-273.

  29. J. Savir and W. McAnney, “A Multiple Seed Linear Feedback Shift Register,” in Proc. of International Test Conference, Sept. 1990, pp. 10-14.

  30. J. Savir, “Distributed Generation ofWeighted Random Patterns,” IEEE Trans. on Computers, vol. 48, no. 12, pp. 1364-1368, 1999.

    Google Scholar 

  31. J. Savir, “Distributed BIST Architecture to Combat Delay Faults,” Journal of Electronic Testing, Theory and Applications, vol. 16, no. 4, pp. 369-380, 2000.

    Google Scholar 

  32. C. Su, “Random Testing of Interconnects in a Boundary Scan Environment,” in Proc. of International Test Conference, 1992, pp. 372-381.

  33. P.H.R. Scholefield, “Shift Registers Generating Maximum-Length Sequences,” Electronic Technology, Oct. 1960, pp. 389-394.

  34. Standard Test Access Port and Boundary Scan Architecture, IEEE Std. 1149.1, 1990.

  35. T. Storey, “A Test Methodology for VLSI Chips on Silicon,” in Proc. of International Test Conference, 1993, pp. 359-368.

  36. D. Sylvester and K. Keutzer, “Getting to the Bottom of Deep Submicron” in Proc. of International Conference on Computer-Aided Design, Nov. 1998, pp. 203-211.

  37. O. Torreiter,U. Goecke, and K. Melocco, “Testing the Enterprise IBM S-390TM Multi Processor,” in Proc. of International Test Conference, 1997, pp. 115-123.

  38. S. Venkataraman, J. Rajski, S. Hellebrand, and S. Tarnick, “An Efficient BIST Scheme Based On Reseeding of Multiple Polynomial Linear Feedback Shift Registers,” in International Conference on Computer-Aided Design, Digest of Technical Papers, Nov. 1993, pp. 7-11.

  39. C.-Y. Wang, S.-W. Tung, and J.-Y. Jou, “On Automatic Verification Pattern Generation for SoC with Port-Order Fault Model,” IEEE Trans. Computer-Aided Design, vol. 21, no. 4, pp. 466-479, 2002.

    Google Scholar 

  40. C.-Y. Wang, S.-W. Tung, and J.-Y. Jou, “Automatic Interconnection Rectification SoC Design Verification Based on the Port-Order Fault Model,” IEEE Trans. Computer-Aided Design, vol. 22, no. 1, pp. 104-114, 2003.

    Google Scholar 

  41. Y. Zorian, “AUniversalTestability Strategy for Multi-Chip Modules Based on BIST and Boundary Scan,” in Proc. International Conf. on Computer Design, 1992, pp. 59-66.

  42. Y. Zorian and H. Bederr, “Designing Self Testable Multi-Chip Modules,” in Proc. of European Test Conference, 1996, pp. 181-185.

  43. Y. Zorian, “A Distributed BIST Control Scheme for Complex VLSI Devices,” Proc. of IEEE VLSI Test Symposium, 1993, pp. 4-9.

Download references

Author information

Authors and Affiliations

  1. Sun Microsystems, 430 North Mary Avenue, Sunnyvale, CA, 94085, USA

    Rajesh Pendurkar

  2. School of Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta, GA, 30332-0250, USA

    Abhijit Chatterjee & Yervant Zorian

Authors
  1. Rajesh Pendurkar
    View author publications

    You can also search for this author in PubMed Google Scholar

  2. Abhijit Chatterjee
    View author publications

    You can also search for this author in PubMed Google Scholar

  3. Yervant Zorian
    View author publications

    You can also search for this author in PubMed Google Scholar

Rights and permissions

Reprints and permissions

About this article

Cite this article

Pendurkar, R., Chatterjee, A. & Zorian, Y. Distributed Diagnosis of Interconnections in SoC and MCM Designs. Journal of Electronic Testing 20, 291–307 (2004). https://doi.org/10.1023/B:JETT.0000029462.95693.9e

Download citation

  • Issue Date:

  • DOI: https://doi.org/10.1023/B:JETT.0000029462.95693.9e

Search

Navigation