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A Note on System-on-Chip Test Scheduling Formulation

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Abstract

While many different formulations of the embedded core test scheduling problem (ECTSP) have been proposed in test literature recently, a single unified presentation of ECTSP in terms of conventional scheduling patterns has been lacking. There exists a large body of literature on multi-processor scheduling which can be directly applied to ECTSP; in this paper the author presents an introduction to scheduling notation and demonstrates the mapping between many important test scheduling problems like power-constrained, precedence constrained, and defect-oriented scheduling to conventional multi-processor job scheduling problems. Two examples are presented to illustrate this mapping. This unified presentation should make the existing body of knowledge in Operations Research scheduling research easily accessible to test engineers and test automation tool developers.

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References

  1. L. Bianco, J. Blażewicz, P. Dell'Olmo, and M. Drozdowski, “Scheduling Multiprocessor Tasks on a Dynamic Configuration of Dedicated Processors,” Annals of Operations Research, vol. 58, pp. 493-517, 1995.

    Google Scholar 

  2. J. Blażewicz, M.Y. Kovalyov, M. Machowiak, D. Trystram, and J.Weglarz, “Scheduling Malleable Tasks on Parallel Processors to Minimize the Makespan,” Proc. of ECCO XIV, May 2001.

  3. P. Brucker, Scheduling Algorithms, 2nd edition, Springer-Verlag, 1997.

  4. J.L. Bruno, E.G. Coffman, and R. Sethi, “Scheduling Independent Tasks to Reduce Mean Finishing Time,” Comm. of the ACM, 1974.

  5. K. Chakrabarty, “Design of System-on-a-Chip Test Access Architectures Under Place-and-Route and Power Constraints,” in Proc.ACM/IEEE DesignAutomation Conf. (DAC), June 2000, pp. 432-437.

  6. K. Chakrabarty, “Test Scheduling for Core-Based Systems Using Mixed-Integer Linear Programming,” IEEE Trans. on CAD, vol. 19, no. 10, pp. 1163-1174, 2000.

    Google Scholar 

  7. K. Chakrabarty, “Optimal Test Access Architectures for Systemon-a-Chip,” ACM Tran. Design Automation of Electronic Systems, vol. 6, pp. 26-49, 2001.

    Google Scholar 

  8. A.N. Choundhary, B. Narhari, D.M. Nicol, and R. Simha, “Optimal Processor Assignment for a Class of Pipelined Computations,” IEEE Trans. Parallel and Distributed Systems, vol. 5, no. 4, pp. 439-445, 1994.

    Google Scholar 

  9. G. Dobson and U.S. Karmakar, “Simultaneous Resource Scheduling to Minimize Weighted Flow Times,” Operations Research, vol. 37, no. 4, pp. 592-600, 1989.

    Google Scholar 

  10. J. Du and J.Y.T. Leung, “Complexity of Scheduling Parallel Task Systems,” SIAM J. Discrete Math., vol. 2, no. 4, pp. 473-487, 1989.

    Google Scholar 

  11. T. Gonzalez and S. Sahni, “Open Shop Scheduling to minimize Finish Time,” Journal of the ACM, vol. 23, pp. 665-679, 1976.

    Google Scholar 

  12. Y. Huang, W.T. Cheng, C.C. Tsai, N. Mukherjee, O. Samman, Y. Zaidan, and S.M. Reddy, “Resource Allocation and Test Scheduling for Concurrent Test of Core-Based SOC Design,” Proc. Asian Test Symposium (ATS), Nov. 2001, pp. 265-270.

  13. IEEE P1500 Web Site, http://grouper.ieee.org/groups/1500/.

  14. V. Iyengar and K. Chakrabarty, “Precedence-Based, Preemptive, and Power-Constrained Test Scheduling for Systemon-a-Chip,” Proceedings IEEE VLSI Test Symposium (VTS), Marina del Rey, CA: IEEE Computer Society Press, May 2001, pp. 368-374.

  15. V. Iyengar, K. Chakrabarty, and E.J. Marinissen, “Test Wrapper and Test Access Mechanism Co-Optimization for System-on-a-Chip,” in Proc. IEEE International Test Conf. (ITC), Oct. 2001, pp. 1023-1032.

  16. W. Jiang and B. Vinnakota, “Defect-Oriented Test Scheduling,” Proc. IEEE VLSI Test Symposium (VTS), April 1999, pp. 433-438.

  17. M. Keating and P. Bricaud, Reuse Methodology Manual For System-on-Chip Designs, Kluwer Academic Publishers, 1998.

  18. S. Koranne, “A Novel Reconfigurable Wrapper for Testing of Embedded Core-Based SOCs and its Associated Scheduling Algorithm,” Journal of Electronic Testing: Theory and Applications, vol. 18, no. 4, pp. 415-434, 2002.

    Google Scholar 

  19. S. Koranne, “Formulating SoC Test Scheduling as a Network Transportation Problem,” IEEE Trans. on CAD, vol. 21, no. 12, pp. 1517-1525, 2002.

    Google Scholar 

  20. S. Koranne, “On Test Scheduling for Core-Based SOCs,” Proc. of VLSI Design/ASP-DAC 2002, Jan. 2002, pp. 505-510.

  21. E. Larsson and Z. Peng, “An Integrated System-on-Chip Test Framework,” Proc. Design, Automation, and Test in Europe (DATE), March 2001, pp. 138-144.

  22. J.K. Lenstra, D.B. Shmoys, and E. Tardos, “Approximation Algorithms for Scheduling Unrelated Parallel Machines,” Proc. 28th Annual IEEE Symposium on Foundations of Computer Science (FOCS), 1987, pp. 217-224.

  23. E.J. Marinissen, S.K. Goel, and M. Lousberg, “Wrapper Design for Embedded Core Test,” in Proc. IEEE International Test Conf. (ITC), Oct. 2000, pp. 911-920.

  24. E.J. Marinissen, V. Iyengar, and K. Chakrabarty, “A Set of Benchmarks for Modular Testing of SOCs,” in Proc. IEEE International Test Conf. (ITC), Oct. 2002, pp. 519-528.

  25. E.J. Marinissen, V. Iyengar, and K. Chakrabarty, ITC'02 SOC Benchmark Website. http://www.extra.research.philips. com/itc02socbenchm/, 2002.

  26. V. Muresan et al., “A Comparison of Classical Scheduling Approaches in Power-Constrained Block-Test Scheduling,” in Proc. IEEE International Test Conf. (ITC), Oct. 2000, pp. 882-891.

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  1. Tanner Research, Inc., Pasadena, CA, USA

    Sandeep Koranne

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  1. Sandeep Koranne
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Koranne, S. A Note on System-on-Chip Test Scheduling Formulation. Journal of Electronic Testing 20, 309–313 (2004). https://doi.org/10.1023/B:JETT.0000029463.01808.5e

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