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A New Approach to the Analysis of Single Event Transients in VLSI Circuits

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Abstract

Single event transients (SETs) on combinational gates are becoming an issue in deep sub-micron technologies, thus efficient and accurate techniques for assessing their impact are strongly required. This paper presents a new technique that embeds time-related information in the topology of the analyzed circuit, allowing evaluating the effects of SETs via zero-delay simulation instead of timed simulation. The analysis of complex designs becomes thus possible at a very limited cost in terms of CPU time. Moreover, circuits enriched with time-related information are suitable for hardware emulation thus allowing further reducing the time for SET-effect analysis, while providing the same accuracy of state-of-the-art approaches based on timed simulations. The paper reports results showing how the proposed method can be effectively used to analyze complex designs.

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Authors and Affiliations

  1. Dipartimento di Automatica e Informatica, Politecnico di Torino, Torino, Italy.

    M. Sonza Reorda

  2. Dipartimento di Automatica e Informatica, Politecnico di Torino, Torino, Italy.

    M. Violante

Authors
  1. M. Sonza Reorda
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  2. M. Violante
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Reorda, M.S., Violante, M. A New Approach to the Analysis of Single Event Transients in VLSI Circuits. Journal of Electronic Testing 20, 511–521 (2004). https://doi.org/10.1023/B:JETT.0000042515.67579.c1

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