Skip to main content
SpringerLink
Log in

Constant Coefficient Multiplication Using Look-Up Tables

  • Published:
Journal of VLSI signal processing systems for signal, image and video technology Aims and scope Submit manuscript

Abstract

Multiplication is an important but expensive operation in most FPGA-based signal processing systems. Many techniques have been introduced for reducing the size and improving the speed of FPGA-based multipliers. Constant-coefficient multipliers are an important class of such multipliers that reduce FPGA resource requirements by exploiting constant-specific optimizations. This paper reviews and analyzes a constant coefficient multiplier that exploits the fine-grain memory resources of FPGAs by performing table look-up. Several optimizations to this multiplier are introduced and analyzed. This paper will also introduce several techniques for reducing the resources of this multiplier by exploiting modern FPGA architectural enhancements.

This is a preview of subscription content, log in via an institution to check access.

Access this article

Log in via an institution

Price excludes VAT (USA)
Tax calculation will be finalised during checkout.

Instant access to the full article PDF.

Institutional subscriptions

Similar content being viewed by others

References

  1. B.L. Hutchings and B. Nelson, “GIGAOP DSP on FPGA,” in Proceedings of the IEEE International Conference on Acoustics, Speech, and Signal Processing (ICASSP), vol. II, 2001, pp. 885-888.

    Google Scholar 

  2. T. Moeller and D.R. Martinez, “Field Programmable Gate Array Based Radar Front-End Digital Signal Processing,” in Proceedings of the IEEE Workshop on FPGAs for Custom Computing Machines, K.L. Pocek and J.M. Arnold (Eds.), Napa, CA: IEEE Computer Society, IEEE, April 1999, pp. 178-187.

    Google Scholar 

  3. M. Shand, P. Bertin, and J. Vuillemin, “Hardware Speedups in Long Integer Multiplication,” Computer Architecture News, vol. 19, no. 1, 1991, pp. 106-114.

    Article  Google Scholar 

  4. L. Louca, T.A. Cook, and W.H. Johnson, “Implementation of IEEE Single Precision Floating Point Addition and Multiplication on FPGAS,” in ACM/SIGDA International Symposium on Field Programmable Gate Arrays, Monterey, CA, Feb. 1996, pp. 107-116.

  5. F. de Dinchin and V. Lefèvre, “Constant Multipliers for FPGAs,” in Proceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications, H.R. Arabnia (Ed.), CSREA Press, June 2000, vol. I, pp. 167-173.

  6. T. Courtney, R. Turner, and R. Woods, “Multiplexer Based Reconfiguration for Virtex Multipliers,” in Field-Programmable Logic and Applications. Proceedings of the 9th International Workshop, FPL 2000, 2000, pp. 749-758.

  7. T. Courtney, R. Turner, and R. Woods, “An Investigation of Reconfigurable Multipliers for use in adaptive Signal Processing,” in Proceedings of the IEEE Symposium on FPGAs for Custom Computing Machines (FCCM'00), IEEE Computer Society Press, April 2000, pp. 341-343.

  8. A.E. Tenca, M.D. Ercegovac, and M.E. Louie, “Fast On-Line Multiplication Units Using LSA Organization,” in Proceedings of the International Society of Optical Engineering (SPIE). Visual Communications and Image Processing. Real-Time Signal Processing, 1999, vol. 3807, pp. 74-83.

    Google Scholar 

  9. R. Bittner and P. Athanas, “Computing Kernels Implemented with a Wormhole RTR CCM,” in Proceedings of IEEE Workshop on FPGAs for Custom Computing Machines, J. Arnold and K.L. Pocek (Eds.), Napa, CA, April 1997, pp. 98-105.

  10. M.J. Wirthlin and B.L. Hutchings, “Improving Functional Density Using Run-Time Circuit Reconfiguration,” IEEE Transaction on Very Large Scale Integration (VLSI) Systems, vol. 6, no. 2, 1998, pp. 247-256.

    Article  Google Scholar 

  11. P. James-Rexby and S.A. Guccione, “Automated-Extraction of Run-Time Parameterisable Cores from Programmable Device Configurations,” in Proceedings of the IEEE Symposium on FPGAs for Custom Computing Machines (FCCM '00), K.L. Pocek and J.M. Arnold (Eds.), IEEE Computer Society Press, April 2000, pp. 153-161.

  12. K. Chapman, “Constant Coefficient Multipliers for the XC4000E,” Technical Report XAPP 054, Xilinx Corporation, Dec. 11, 1996. Version 1.1.

  13. K.D. Chapman, “Fast Integer Multipliers Fit in FPGA's,” EDN, May 12, 1994, pp. 79-80.

  14. M.J. Wirthlin and B. McMurtrey, “Efficient Coefficient Multiplication Using Advanced FPGA Architectures,” in Field-Programmable Logic and Applications. Proceedings of the 11th International Workshop, FPL 2001, Lecture Notes in Computer Science, Springer-Verlag, Aug. 2001, pp. 555-564.

Download references

Author information

Authors and Affiliations

  1. Department of Electrical and Computer Engineering, Brigham Young University, 459 Clyde Building, Provo, UT, 84602, USA

    Michael J. Wirthlin

Authors
  1. Michael J. Wirthlin
    View author publications

    You can also search for this author in PubMed Google Scholar

Rights and permissions

Reprints and permissions

About this article

Cite this article

Wirthlin, M.J. Constant Coefficient Multiplication Using Look-Up Tables. The Journal of VLSI Signal Processing-Systems for Signal, Image, and Video Technology 36, 7–15 (2004). https://doi.org/10.1023/B:VLSI.0000008066.95259.b8

Download citation

  • Published:

  • Issue Date:

  • DOI: https://doi.org/10.1023/B:VLSI.0000008066.95259.b8

Search

Navigation