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Instruction Scheduling for Low Power

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Abstract

Reducing energy consumption has become an important issue in designing hardware and software systems in recent years. Although low power hardware components are critical for reducing energy consumption, the switching activity, which is the main source of dynamic power dissipation in electronic systems, is largely determined by the software running on these systems.

In this paper, we present and evaluate several instruction scheduling algorithms that reorder a given sequence of instructions taking into account the energy considerations. We first compare a performance-oriented scheduling technique with three energy-oriented instruction scheduling algorithms from both performance (execution cycles of the resulting schedules) and energy consumption points of view. Then, we propose three scheduling algorithms that consider energy and performance at the same time. Our experimentation with these scheduling techniques shows that the best scheduling from the performance perspective is not necessarily the best scheduling from the energy perspective. Further, scheduling techniques that consider both energy and performance simultaneously are found to be desirable, that is, these techniques are quite successful in reducing energy consumption and their performance (in terms of execution cycles) is comparable to that of a pure performance-oriented scheduling. We also illuminate the inherent approximations and difficulties in building energy models for enabling energy-aware instruction scheduling and explore alternative options using cycle-accurate energy simulator. The simulation results show that the energy-oriented scheduling reduces energy consumption by up to 30% compared to the performance-oriented scheduling.

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Authors and Affiliations

  1. Department of Computer Science and Engineering, The Pennsylvania State University, University Park, PA, 16802, USA

    A. Parikh, Soontae Kim, M. Kandemir, N. Vijaykrishnan & M.J. Irwin

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  1. A. Parikh
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  2. Soontae Kim
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  3. M. Kandemir
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  4. N. Vijaykrishnan
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  5. M.J. Irwin
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Parikh, A., Kim, S., Kandemir, M. et al. Instruction Scheduling for Low Power. The Journal of VLSI Signal Processing-Systems for Signal, Image, and Video Technology 37, 129–149 (2004). https://doi.org/10.1023/B:VLSI.0000017007.28247.f6

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  • DOI: https://doi.org/10.1023/B:VLSI.0000017007.28247.f6

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