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Complex ±1 Multiplier Based on Signed-Binary Transformations

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Abstract

A complex ±1 multiplier is an integral element in modern CDMA communication systems, specifically as a pseudonoise code scrambler/descrambler. An efficient implementation is essential to reduce the critical path delay, power, and area of wireless receivers. A signed-binary architecture is proposed to achieve this complex multiplier function. Tradeoffs and design solutions are discussed. It is shown that the VLSI circuit implementation of the arithmetic operations may be significantly improved by using non-conventional number representations and transforming intermediate results from one format to another format. For a target function, the objective is to change the number representations of the input and output operands such that a minimum amount of logic circuitry is required to achieve a computation. An analytical framework is developed that expands the scope of the functions that can be efficiently implemented using signed-binary representation. Simulations exhibit a significant speed improvement as compared to alternative architectures.

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Authors and Affiliations

  1. Department of Electrical and Computer Engineering, University of Rochester, Rochester, New York, 14627, USA

    Boris D. Andreev, Edward L. Titlebaum & Eby G. Friedman

Authors
  1. Boris D. Andreev
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  2. Edward L. Titlebaum
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  3. Eby G. Friedman
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Andreev, B.D., Titlebaum, E.L. & Friedman, E.G. Complex ±1 Multiplier Based on Signed-Binary Transformations. The Journal of VLSI Signal Processing-Systems for Signal, Image, and Video Technology 38, 13–24 (2004). https://doi.org/10.1023/B:VLSI.0000028530.88948.36

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  • DOI: https://doi.org/10.1023/B:VLSI.0000028530.88948.36

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