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QVGA/CIF Resolution MPEG-4 Video Codec Based on a Low-Power and General-Purpose DSP

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Abstract

This paper describes a quarter video graphic array/common intermediate format (QVGA/CIF) resolution MPEG-4 video codec based on a low-power, general-purpose digital signal processor (DSP) (NEC μPD77210, 160 MHz, 80 mW, 1.5 V). To enhance video codec performance, the codec employs fast algorithms, including, in motion estimation, a successive similarity detection algorithm (SSDA; a fast block matching) whose decision timing for termination of block matching is optimized. Further, the use of a software direct memory access (DMA) queue reduces the wasteful DSP wait cycles that can result from massive access to external frame memories. The resulting codec executes QVGA (320 × 240 pixels) × 15 fps codec, or CIF (352 × 288 pixels) × 15 fps encoding at 384 kbps, in real time, performance levels sufficient for next-generation wireless videotelephony.

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Authors and Affiliations

  1. Media and Information Research Laboratories, 1753, Shimonumabe, Nakaharaku, Kawasaki, 211-8666, Japan

    Atsushi Hatabu, Takashi Miyazaki & Ichiro Kuroda

Authors
  1. Atsushi Hatabu
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  2. Takashi Miyazaki
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  3. Ichiro Kuroda
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Hatabu, A., Miyazaki, T. & Kuroda, I. QVGA/CIF Resolution MPEG-4 Video Codec Based on a Low-Power and General-Purpose DSP. The Journal of VLSI Signal Processing-Systems for Signal, Image, and Video Technology 39, 7–14 (2005). https://doi.org/10.1023/B:VLSI.0000047268.39953.60

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  • DOI: https://doi.org/10.1023/B:VLSI.0000047268.39953.60

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