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Abstract

Real-time 3D Graphics rendering consumes significant power because of its very high computation and memory access rate. Due to variation in workload and perceptual tolerance, power-awareness can optimize this power consumption significantly, thus facilitating migration to future power-constrained devices such as personal digital assistants (PDAs), tablets, wearables, phones etc. This work proposes such a low power system based on Approximate Graphics Rendering (AGR). The AGR system supports various algorithms and incremental changes to the computational mechanism based on certain pre-specified parameters. The knowledge available apriori about the signal and noise models of graphic images and Human Visual Perception (HVP) are used to select the configuration that meets the quality needs at the lowest power consumption.

The power savings using the AGR system are examined for two power hungry stages of the 3D graphics rendering system, namely shading and texture mapping. Besides supporting various algorithms, two novel parameterizable computation schemes are proposed. First, iterative COordinate Rotation DIgital Computer (CORDIC) algorithm based units are incorporated for certain computations. Second, a scheme for dynamically enhancing the perceived image spatial correlation for reduced computations is presented.

A hardware synthesis and estimation methodology based on realistic graphics content from the well-known 3D graphics benchmarks and the game Quake2 [1] is used for estimation of power savings. Significant power savings of 75.1%, 73.8% and 72% are demonstrated in the shading, texture mapping function blocks and CORDIC based 3D vector interpolator respectively.

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References

  1. ID software, http://www.idsoftware.com/games/quake/quake/.

  2. “Digital domain,” http://www.d2.com/.

  3. “VRML consortium,” http://www.vrml.org/.

  4. “Buzz 3D-PC,” http://www.vrmarketing.com/buzz3d/b3d. Index.htm/.

  5. A. Chandrakasan and R. Brodersen, “Low Power Digital CMOS Design,” Journal of Solid-State Circuits,vol. 27, 1992, pp. 473–484.

    Article  Google Scholar 

  6. R. Graybill and R. Melhem, Power Aware Computing, Kluwer Academic/Plenum Publishers, May 2002.

  7. J. Rabacy, “Reconfigurable Processing: The Solution to Low Power Programmable DSP,” in International Conference on Acoustics, Speech, and Signal Processing, 1997.

  8. W. Burleson et al., “Dynamically Parameterized Algorithms and Architectures to Exploit Signal Variations for Improved Performance and Reduced Power,” in International Conference on Acoustics, Speech, and Signal Processing, 2001.

  9. T. Moller and E. Haines, Real-Time Rendering.AKPeters, 1999.

  10. S. Nawab, A. Oppenheim, A. Chandrakasan, J. Winograd, and J. Ludwig, “Approximate Signal Processing,” VLSI Signal Processing, vol. 15, nos. 1-2, 1997, pp. 177–200.

    Article  Google Scholar 

  11. A. Sinha, A. Wang, and A. Chandrakasan, “Algorithmic Trans-forms for Efficient Energy Scalable Computation,” in International Symposium on Low Power Electronics and Design (ISLPED), Aug. 2000.

  12. M. Reddy, “Perceptually Optimized 3D Graphics,” IEEE Computer Graphics and Applications,vol. 21, no. 5, Sept./Oct. 2001, pp. 68–75.

    Article  Google Scholar 

  13. D. Kelly, “Motion and Vision II: Stabilized Spatio-Temporal Threshold Surface,” Journal of the Optical Society of America, vol. 79, no. 10, Oct. 1979, pp. 1340–1349.

    Article  Google Scholar 

  14. C.J. van den Branden Lambrecht, “A Working Spatio-Temporal Model of Human Visual System for Image Restoration and Quality Assesment Applications,” in International Conference on Acoustics Speech and Signal Processing, May 1996.

  15. R. Pajarola and J. Rossignac, “Compressed Progressive Meshes,” IEEE Transactions on Visualization and Computer Graphics,vol. 6, no. 1, 2000, pp. 79–93.

    Article  Google Scholar 

  16. J. Cohen, M. Olano, and D. Manocha, “Appearance-Preserving Simplification,” in SIGGRAPH'98, July 1998, pp. 115–122.

  17. A. Gueziec, G. Taubin, F. Lazarus, and W. Horn, “Simplical Maps for Progressive Transmission of Polygonal Surfaces,” in VRML' 98, Feb. 1998.

  18. H. Hoppe, “Progressive Meshes,” in SIGGRAPH' 96, July 1998, pp. 99–108.

  19. H. Yee, S. Pattanaik, and D. Greenberg, “Spatiotemporal Sensitivity and Visual Attention for Efficient Rendering of Dynamic Environments,” ACM Transactions on Graphics,vol. 20, no. 1, Jan. 2001, pp. 39–65.

    Article  Google Scholar 

  20. R. Dumont, F. Pellacini, and J. Ferwerda, “APerceptually-Based Texture Caching Algorithm for Hardware-Based Rendering,” in Eurographics Workshop on Graphics Rendering, June 2001, pp. 249–256.

  21. T. McReynolds, T. Blythe, B. Grantham, and S. Nelson, “Programming With OpenGL: Advanced Techniques,” in SIGGRAPH' 98, July 1998.

  22. J. Snyder and J. Lengyel, “Visibility sorting and Compositing Without Splitting for Image Layer Decomposition,” in SIGGRAPH' 96, July 1996, pp. 219–230.

  23. J. Euh and W. Burleson, “Exploiting Content-Variation and Perception in Power-Aware 3D Graphics Rendering,” in Power Aware Computer Systems, LNCS: Springer, 2000, pp. 51–64.

    Google Scholar 

  24. J. Euh, J. Chittamuru, and W. Burleson, “A Low Power Content-Adaptive Texture Mapping Architecture for Real-Time 3D Graphics,” in Power Aware Computer Systems, LNCS: Springer, 2002.

    Google Scholar 

  25. O. Mencer, L. Semeria, M. Morf, and J. Delosme, “Application of Reconfigurable CORDIC Architectures,” The Journal of VLSI Signal Processing, Special Issue on Reconfigurable Computing, March 2000.

  26. C. Clarke and G. Nudd, “A Redundant Arithmetic CORDIC System with a Unit Scale Factor,” in IMA Conference on Mathematics in Signal Processing III, 1994, pp. 63–73.

  27. J. Blinn, “Simulation of Wrinkled Surfaces,” in SIGGRAPH' 78, 1978, vol. 12, pp. 286–292.

    Article  Google Scholar 

  28. A. Nannarelli, “Low Power Division and Square-Root,” Ph.D, Dissertation, U.C. Irvine, 1999.

  29. J. Torborg and J. Kajiya, “Talisman: Commodity Real-Time 3D Graphics for the PC,” in TISIGGRAPH, 1996, pp. 353–364.

  30. H. Shin, J. Lee, and L. Kim, “A Minimized hardware Architecture of Fast Phong Shader using Taylor Series Approximation in 3D Graphics,” in IEEE International Conference on Computer Design, Oct. 1998, pp. 286–291.

  31. T. Cormen, C. Leiserson, and R. Rivest, Introduction to Algorithms, McGraw-Hill, 1990.

  32. C. Schlick, Graphics Gems IV,APProfessional, 1994.

  33. B. Phong, “Illumination for Computer Generated Pictures,” Communications of the ACM (CACM), June 1975, pp. 311–317

  34. T. Ikedo and J. Ma, “The Truga001: A Scalable Rendering Processor,” IEEE Computer Graphics and Applications,vol. 18, no. 2, April 1998, pp. 59–79.

    Article  Google Scholar 

  35. J. Euh, J. Chittamuru, and W. Burleson, “CORDIC Based Vector Interpolator for 3D Graphics,” in IEEE Workshop on Signal Processing Systems, Oct. 2002, pp. 240–245.

  36. A. Beers, M. Agrawala, and N. Chaddha, “Rendering From Compressed Textures,” SIGGRAPH' 96, 1996, pp. 373–378.

  37. A. Kugler, “Designing a High-Performance Texturing Circuit,” in Proceedings of the Electronic Imaging Symposium on Multi-media Hardware Architectures, Feb. 1997.

  38. Z. Hakura and A. Gupta, “The Design and Analysis of a Cache Architecture for Texture Mapping,” in 24th International Symposium on Computer Architecture, 1997, pp. 108–120.

  39. M. Cox, N. Bhandari, and M. Shantz, “Multi-Level Texture Caching for 3D Graphics Hardware,” in 25th International Symposium on Computer Architecture, June 1998, pp. 86–97.

  40. H. Igehy, M. Eldridge, and K. Proudfoot, “Prefetching in a Texture Cache Architecture,” in Eurographics/SIGGRAPH Workshop on Graphics Hardware, 1998, pp. 133–142.

  41. A. Rosman and M. Pimpalkhare, “Adaptive Tri-Linear Interpolation for Use When Switching to a New Level-of-Detail Map,” United States Patent: US 6,184,894 B1, Feb. 2001.

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Euh, J., Chittamuru, J. & Burleson, W. Power-Aware 3D Computer Graphics Rendering. The Journal of VLSI Signal Processing-Systems for Signal, Image, and Video Technology 39, 15–33 (2005). https://doi.org/10.1023/B:VLSI.0000047269.03965.e9

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  • DOI: https://doi.org/10.1023/B:VLSI.0000047269.03965.e9

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