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A Scalable System Architecture for High-Throughput Turbo-Decoders

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Abstract

The need for higher data rates is ever rising as wireless communications standards move from the third to the fourth generation. Turbo-Codes are the prevalent channel codes for wireless systems due to their excellent forward error correction capability. So far research has mainly focused on components of high throughput Turbo-Decoders. In this paper we explore the Turbo-Decoder design space anew, both under system design and deep-submicron implementation aspects.

Our approach incorporates all levels of design, from I/O behavior down to floorplaning taking deep-submicron effects into account. Its scalability allows to derive optimized architectures tailored to the given throughput and target technology. We present results for 3GPP compliant Turbo-Decoders beyond 100 Mbit/s synthesized on a 0.18 μm standard cell library.

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Authors and Affiliations

  1. Microelectronic System Design Research Group, University of Kaiserslautern, Erwin-Schroedinger-Strasse, 67663, Kaiserslautern, Germany

    Michael J. Thul, Frank Gilbert, Timo Vogt, Gerd Kreiselmaier & Norbert Wehn

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  1. Michael J. Thul
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  2. Frank Gilbert
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  3. Timo Vogt
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  4. Gerd Kreiselmaier
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  5. Norbert Wehn
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Thul, M.J., Gilbert, F., Vogt, T. et al. A Scalable System Architecture for High-Throughput Turbo-Decoders. The Journal of VLSI Signal Processing-Systems for Signal, Image, and Video Technology 39, 63–77 (2005). https://doi.org/10.1023/B:VLSI.0000047272.75049.0e

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  • DOI: https://doi.org/10.1023/B:VLSI.0000047272.75049.0e

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