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Interleaving on Parallel DSP Architectures

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Abstract

Today's communications systems especially in the field of wireless communications rely on many different algorithms to provide applications with constantly increasing data rates and higher quality. This development combined with the wireless channel characteristics as well as the invention of turbo codes has particularly increased the importance of interleaver algorithms. In this paper, we demonstrate the feasibility to exploit the hardware parallelism in order to accelerate the interleaving procedure. Based on a heuristic algorithm, the possible speedup for different interleavers as a function of the degree of parallelism of the hardware is presented. The parallelization is generic in the sense that the assumed underlying hardware is based on a parallel datapath DSP architecture and therefore provides the flexibility of software solutions.

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Authors and Affiliations

  1. Chair for Mobile Communications Systems, Dresden University of Technology, 01062, Dresden, Germany

    Thomas Richter & Gerhard P. Fettweis

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  1. Thomas Richter
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  2. Gerhard P. Fettweis
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Richter, T., Fettweis, G.P. Interleaving on Parallel DSP Architectures. The Journal of VLSI Signal Processing-Systems for Signal, Image, and Video Technology 39, 161–173 (2005). https://doi.org/10.1023/B:VLSI.0000047278.94280.c3

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  • DOI: https://doi.org/10.1023/B:VLSI.0000047278.94280.c3

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