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Characterization and Evaluation of Cache Hierarchies for Web Servers

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Abstract

As Internet usage continues to expand rapidly, careful attention needs to be paid to the design of Internet servers for achieving high performance and end-user satisfaction. Currently, the memory system continues to remain a significant performance bottleneck for Internet servers employing multi-GHz processors. In this paper, our aim is two-fold: (1) to characterize the cache/memory performance of web server workloads and (2) to propose and evaluate cache design alternatives for future web servers. We chose SPECweb99 as the representative web server workload and our entire characterization and evaluation methodology is based on our CASPER simulation framework. We begin by exploring the processor cache design space for single and dual-processor servers. Based on our observations, we then evaluate other cache hierarchy alternatives such as chipset caches, coherence filters and decompressed page stores. We show the sensitivity of these components to basic organization parameters such as cache size, line size and degree of associativity. We also present the performance implications of routing memory requests initiated by I/O devices through these caches. Based on detailed simulation data and its implications on system level performance, this paper shows that chipset caches have significant potential for improving future web server performance.

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  1. Intel Corporation, 2111 NE 25th Avenue, M/S JF3-232, Hillsboro, OR, 97124, USA

    Ravi Iyer

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  1. Ravi Iyer
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Iyer, R. Characterization and Evaluation of Cache Hierarchies for Web Servers. World Wide Web 7, 259–280 (2004). https://doi.org/10.1023/B:WWWJ.0000028180.97418.53

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