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  4. A technology mapper for depth-constrained FPGA logic cells
 
conference paper

A technology mapper for depth-constrained FPGA logic cells

Jiang, Zhenghong
•
Zgheib, Grace  
•
Colin Yu Lin
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2015
2015 25th International Conference on Field Programmable Logic and Applications (FPL)
  • Details
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Type
conference paper
DOI
10.1109/FPL.2015.7294014
Author(s)
Jiang, Zhenghong
•
Zgheib, Grace  
•
Colin Yu Lin
•
Novo, David  
•
Huang, Zhihong
•
Yang, Liqun
•
Yang, Haigang
•
Ienne, Paolo  
Date Issued

2015

Published in
2015 25th International Conference on Field Programmable Logic and Applications (FPL)
Start page

1

End page

8

Editorial or Peer reviewed

REVIEWED

Written at

EPFL

EPFL units
LAP  
Available on Infoscience
January 20, 2023
Use this identifier to reference this record
https://infoscience.epfl.ch/handle/20.500.14299/194145
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