Real-time field programmable gate array architecture for computer vision

Miguel Arias-Estrada; Cesar Torres-Huitzil

doi:10.1117/1.1329341

1 January 2001 Real-time field programmable gate array architecture for computer vision

Miguel Arias-Estrada, Cesar Torres-Huitzil

Journal of Electronic Imaging, Vol. 10, Issue 1, (January 2001). https://doi.org/10.1117/1.1329341

This paper presents an architecture for real-time generic convolution of a mask and an image. The architecture is intended for fast low-level image processing. The field programmable gate array (FPGA)-based architecture takes advantage of the availability of registers in FPGAs to implement an efficient and compact module to process the convolutions. The architecture is designed to minimize the number of accesses to the image memory and it is based on parallel modules with internal pipeline operation in order to improve its performance. The architecture is prototyped in a FPGA, but it can be implemented on dedicated very-large-scale-integrated devices to reach higher clock frequencies. Complexity issues, FPGA resources utilization, FPGA limitations, and real-time performance are discussed. Some results are presented and discussed.

©(2001) Society of Photo-Optical Instrumentation Engineers (SPIE)

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Miguel Arias-Estrada and Cesar Torres-Huitzil "Real-time field programmable gate array architecture for computer vision," Journal of Electronic Imaging 10(1), (1 January 2001). https://doi.org/10.1117/1.1329341

Published: 1 January 2001

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