Real-time algorithm enabling high dynamic range imaging and high frame rate exploitation for custom CMOS image sensor system implemented by FPGA with co-processor

Blake C. Jacquot; Nathan Johnson-Williams

doi:10.1117/12.2077727

27 February 2015 Real-time algorithm enabling high dynamic range imaging and high frame rate exploitation for custom CMOS image sensor system implemented by FPGA with co-processor

Blake C. Jacquot, Nathan Johnson-Williams

Author Affiliations +

Proceedings Volume 9400, Real-Time Image and Video Processing 2015; 940004 (2015) https://doi.org/10.1117/12.2077727
Event: SPIE/IS&T Electronic Imaging, 2015, San Francisco, California, United States

Abstract

We present results from a prototype CMOS camera system implementing a multiple sampled pixel level algorithm (“Last Sample Before Saturation”) in real-time to create High-Dynamic Range (HDR) images that approach the dynamic range of CCDs. The system is built around a commercial 1280 × 1024 CMOS image sensor with 10-bits per pixel and up to 500 Hz full frame rate with higher frame rates available through windowing. We provide details of system architecture and present images collected with the system.

Citation Download Citation

Blake C. Jacquot and Nathan Johnson-Williams "Real-time algorithm enabling high dynamic range imaging and high frame rate exploitation for custom CMOS image sensor system implemented by FPGA with co-processor", Proc. SPIE 9400, Real-Time Image and Video Processing 2015, 940004 (27 February 2015); https://doi.org/10.1117/12.2077727

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