SCC-100 parallel processor for real-time imaging

William J. Jacobi; William B. Kendall; Leo A. Wadsworth

doi:10.1117/12.24131

1 September 1990 SCC-100 parallel processor for real-time imaging

William J. Jacobi, William B. Kendall, Leo A. Wadsworth

Proceedings Volume 1360, Visual Communications and Image Processing '90: Fifth in a Series; (1990) https://doi.org/10.1117/12.24131
Event: Visual Communications and Image Processing '90, 1990, Lausanne, Switzerland

Abstract

The SCC-100 parallel processor utilizes a fully-programmable, 32-bit MIMD architecture optimized for image and signal processing. Applications include image registration, clutter suppression, velocity filtering, multispectral processing, medical imaging and computer vision research as well as radar and sonar signal processing. The first SCC-100 processor, with 19 nodes and a peak throughput in excess of 1 GFLOPS, was recently delivered. A micro-miniature version using hybrid wafer-scale integration is currently under development for space applications.

Citation Download Citation

William J. Jacobi, William B. Kendall, and Leo A. Wadsworth "SCC-100 parallel processor for real-time imaging", Proc. SPIE 1360, Visual Communications and Image Processing '90: Fifth in a Series, (1 September 1990); https://doi.org/10.1117/12.24131

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