Principal devices and hardware volume estimation for moving picture decoder for digital storage media

Makiko Konoshima; Osamu Kawai; Kiichi Matsuda

doi:10.1117/12.24171

1 September 1990 Principal devices and hardware volume estimation for moving picture decoder for digital storage media

Makiko Konoshima, Osamu Kawai, Kiichi Matsuda

Proceedings Volume 1360, Visual Communications and Image Processing '90: Fifth in a Series; (1990) https://doi.org/10.1117/12.24171
Event: Visual Communications and Image Processing '90, 1990, Lausanne, Switzerland

Abstract

The ISO/MPEG has been discussing the establishment of a standard for moving- picture coding to ensure that digital storage media can store picture information efficiently. This paper introduces a trial design for the source decoder of simulation model 2 in the ISO/MPEG video subgroup. This paper describes MPEG simulation model decoding and the Fujitsu video signal processors, VSP-1 and DCT LSI chips. We designed a source decoder using these two LSI chips, memory, and standard logic ICs. The trial design showed that three VSP-ls and one DCT LSI chips are sufficient to make a source decoder.

Citation Download Citation

Makiko Konoshima, Osamu Kawai, and Kiichi Matsuda "Principal devices and hardware volume estimation for moving picture decoder for digital storage media", Proc. SPIE 1360, Visual Communications and Image Processing '90: Fifth in a Series, (1 September 1990); https://doi.org/10.1117/12.24171

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