An area-efficient VLSI architecture for AVS intra frame encoder

Ke Zhang; Lu Yu

doi:10.1117/12.703475

29 January 2007 An area-efficient VLSI architecture for AVS intra frame encoder

Ke Zhang, Lu Yu

Proceedings Volume 6508, Visual Communications and Image Processing 2007; 650822 (2007) https://doi.org/10.1117/12.703475
Event: Electronic Imaging 2007, 2007, San Jose, CA, United States

Abstract

In this paper, we propose a VLSI architecture for AVS intra frame encoder. Reconstruction loop hinders the parallelism exploration and becomes the critical path in an intra frame encoder. A First Selection Then Prediction (FSTP) method is proposed to break the loop and enable the parallel process of intra mode selection and reconstruction on neighboring blocks. In addition, area-efficient modules were developed. Configurable intra predictor can support all the intra prediction modes. A CA-2D-VLC engine with an area-efficient Exp-Golomb encoder was developed to meet the encoding speed demand with comparably low hardware cost. Synthesized with 0.18 m CMOS standard-cell library, the overall hardware cost of the proposed intra frame encoder is 89k logic gates at the clock frequency constraint of 125MHz. Proposed encoder can satisfy real time encoding of 720x576 4:2:0 25fps video at the working frequency of 54MHz.

Citation Download Citation

Ke Zhang and Lu Yu "An area-efficient VLSI architecture for AVS intra frame encoder", Proc. SPIE 6508, Visual Communications and Image Processing 2007, 650822 (29 January 2007); https://doi.org/10.1117/12.703475

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