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Applications of modular summation codes to concurrent error detection systems for combinational boolean circuits

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Abstract

We establish new properties of modular summation codes that allow for an efficient use of these codes to organize concurrent error detection (CED) systems for combinational logical circuits with unidirectionally independent outputs. We compare the properties of modular summation codes and classical Berger codes. We obtain conditions for the construction of combinational logical circuits with detection of all single faults based on modular summation codes.

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References

  1. Sogomonyan, E.S. and Slabakov, E.V., Samoproveryaemye ustroistva i otkazoustoichivye sistemy (Self-Testing Devices and Fault-Tolerant Systems), Moscow: Radio i Svyaz’, 1989

    Google Scholar 

  2. Sapozhnikov, V.V. and Sapozhnikov, Vl.V., Samoproveryaemye diskretnye ustroistva (Self-Testing Discrete Devices), St. Petersburg: Energoatomizdat, 1992.

    Google Scholar 

  3. Goessel, M. and Graf, S., Error Detection Circuits, London: McGraw-Hill, 1994

    Google Scholar 

  4. Pradhan, D.K., Fault-Tolerant Computer System Design, Upper Saddle River: Prentice Hall, 1996

    Google Scholar 

  5. Sapozhnikov, V.V., Sapozhnikov, Vl.V., Gessel’, M., and Morozov, A.A., A Method for Constructing Combinational Self-Testing Devices with Detection of All Single Faults, Elektron. Modelir., 1998, vol. 20, no. 6, pp. 70–80.

    Google Scholar 

  6. Goessel, M., Morozov, A.A., Sapozhnikov, V.V., and Sapozhnikov, Vl.V., Study of Combinational Self-Checking Devices with Independent and Monotonic Independent Outputs, Autom. Remote Control, 1997, vol. 58, no. 2, part 2, pp. 299–309.

    MATH  Google Scholar 

  7. Berger, J.M., A Note on Error Detection Codes for Asymmetric Channels, Inform. Control, 1961, vol. 4, no. 1, pp. 68–73.

    Article  MATH  Google Scholar 

  8. Lo, J.-C, Thanawastien, S., and Nicolaidis, M., An SFS Berger Check Prediction ALU and Its Application to Self-checking Processor Designs, Comput.-Aided Design Integrat. Circuits Syst., 1992, vol. 11, no. 4, pp. 525–540.

    Article  Google Scholar 

  9. Jha, N.K. and Wang, S.J., Design and Synthesis of Self-Checking VLSI Circuits, IEEE Trans. Comput.-Aided Design, 1993, vol. 12, no. 6, pp. 878–887.

    Article  Google Scholar 

  10. De, K., Natarajan, C., Nair, D., and Banerjee, P., RSYN: A System for Automated Synthesis of Reliable Multilevel Circuits, IEEE Trans. VLSI Syst., 1994, vol. 2, no. 2, pp. 186–195.

    Article  Google Scholar 

  11. Gessel, M., Sapozhnikov, V.V., and Sapozhnikov, Vl.V., Construction of Combination Self-Checking Devices with Monotonically Independent Outputs, Autom. Remote Control, 1994, vol. 55, no. 7, part 2, pp. 1050–1059.

    MATH  Google Scholar 

  12. Gorshe, S. and Bose, B., A Self-Checking ALU Design with Efficient Codes, Proc. VLSI Test Symp., 1996, pp. 157–161.

    Chapter  Google Scholar 

  13. Saposhnikov, V.V., Saposhnikov, Vl.V., Morosov, A., and Göessel, M., Design of Self-Checking Unidirectional Combinational Circuits with Low Area Overhead, Proc. IEEE Int. On-Line Testing Workshop (IOLTW), Biarritz, France, 1996, pp. 56–67.

    Google Scholar 

  14. Morosov, A., Saposhnikov, V.V., Saposhnikov, Vl.V., and Goessel, M., Self-Checking Combinational Circuits with Unidirectionally Independent Outputs, VLSI Design, 1998, vol. 5, no. 4, pp. 333–345.

    Article  Google Scholar 

  15. Saposhnikov, V.V., Morosov, A., Saposhnikov, Vl.V., and Göessel, M., A New Design Method for Self-Checking Unidirectional Combinational Circuits, J. Electron. Testing: Theory Appl., 1998, vol. 12, nos. 1–2 (February/April), pp. 41–53.

    Google Scholar 

  16. Morozov, A., Saposhnikov, V.V., Saposhnikov, Vl.V., and Goessel, M., New Self-Checking Circuits by Use of Berger-codes, 6th IEEE Int. On-Line Testing Workshop, Palma de Mallorca, Spain, 2000, pp. 141–146.

    Google Scholar 

  17. Göessel, M., Ocheretny, V., Sogomonyan, E., and Marienfeld, D., New Methods of Concurrent Checking, Dordrecht: Springer Science+Business Media B.V., 2008, 1st ed.

    Google Scholar 

  18. Marouf, M.A. and Friedman, A.D., Design of Self-Checking Checkers for Berger Codes, Proc. 8 Ann. Int. Conf. Fault-Tolerant Comput., Toulouse, 1978, vol. C-27, pp. 179–183.

    Google Scholar 

  19. Mel’nikov, A.G., Sapozhnikov, V.V., and Sapozhnikov, Vl.V., Synthesis of Self-Checking Checkers for Summation Codes, Probl. Peredachi Inf., 1986, vol. XXII, no. 2, pp. 85–97.

    Google Scholar 

  20. Piestrak, S.J., Design of Self-Testing Checkers for Unidirectional Error Detecting Codes, Wroc-law: Oficyna Wydawnicza Politechniki Wroc-lavskiej, 1995

    Google Scholar 

  21. Sogomonyan, E.S., Design of Built-In Self-Checking Monitoring Circuits for Combinational Devices, Autom. Remote Control, 1974, vol. 35, no. 2, part 2, pp. 280–289.

    Google Scholar 

  22. Busaba, F.Y. and Lala, P.K., Self-Checking Combinational Circuit Design for Single and Unidirectional Multibit Errors, J. Electron. Testing: Theory Appl., 1994, no. 5, pp. 19–28.

    Article  Google Scholar 

  23. Saposhnikov, V., Saposhnikov, Vl., Goessel, M., and Morosov, A., A Method of Construction of Combinational Self-Checking Units with Detection of all Single Faults, Eng. Simul., 1999, vol. 16, pp. 745–756.

    Google Scholar 

  24. Bose, B. and Lin, D.J., Systematic Unidirectional Error-Detection Codes, IEEE Trans. Comput., 1985, vol. C-34. Nov, pp. 1026–1032.

    Article  Google Scholar 

  25. Kavousianos, X. and Nikolos, D., Novel TSC Checkers for Bose-Lin and Bose Codes, Proc. 3rd IEEE Int. On-Line Testing Workshop, July 6–8, 1998, Capry, Italy, pp. 172–176.

    Google Scholar 

  26. Efanov, D.V., Sapozhnikov, V.V., and Sapozhnikov, Vl.V., On Summation Code Properties in Functional Control Circuits, Autom. Remote Control, 2010, vol. 71, no. 6, pp. 1117–1123.

    Article  MATH  MathSciNet  Google Scholar 

  27. Blyudov, A., Efanov, D., Sapozhnikov, V., and Sapozhnikov, Vl., Properties of Code with Summation for Logical Circuit Test Organization, Proc. 10 IEEE East-West Design & Test Symposium (EWDTS‘2012), Kharkov, Ukraine, September 14–17, 2012, pp. 114–117.

    Google Scholar 

  28. Blyudov, A.A., Efanov, D.V., Sapozhnikov, V.V., and Sapozhnikov, Vl.V., Summation Codes for Organization of Control of Combinational Circuits, Autom. Remote Control, 2013, vol. 74, no. 6, pp. 1020–1028.

    Article  MATH  Google Scholar 

  29. Blyudov, A.A., Efanov, D.V., Sapozhnikov, V.V., and Sapozhnikov, Vl.V., Construction of a Modified Berger Code with Minimal Number of Undetectable Errors in Information Bits, Elektron. Modelir., 2012, vol. 34, no. 6, pp. 17–29.

    Google Scholar 

  30. Ghosh, S., Basu, S., and Touba, N.A., Synthesis of Low Power CED Circuits Based on Parity Codes, Proc. 23rd IEEE VLSI Test Sympos. (VTS’05), 2005, pp. 315–320.

    Google Scholar 

  31. Fujiwara, E., Code Design for Dependable Systems: Theory and Practical Applications, New York: Wiley, 2006

    Book  Google Scholar 

  32. Sapozhnikov, V.V. and Sapozhnikov, Vl.V., Osnovy tekhnicheskoi diagnostiki (Foundations of Technical Diagnostics), Moscow: Marshrut, 2004.

    Google Scholar 

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Authors and Affiliations

  1. Petersburg State Transport University, St. Petersburg, Russia

    D. V. Efanov, V. V. Sapozhnikov & Vl. V. Sapozhnikov

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  1. D. V. Efanov
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  2. V. V. Sapozhnikov
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  3. Vl. V. Sapozhnikov
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Correspondence to D. V. Efanov.

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Original Russian Text © D.V. Efanov, V.V. Sapozhnikov, Vl.V. Sapozhnikov, 2015, published in Avtomatika i Telemekhanika, 2015, No. 10, pp. 152–169.

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Efanov, D.V., Sapozhnikov, V.V. & Sapozhnikov, V.V. Applications of modular summation codes to concurrent error detection systems for combinational boolean circuits. Autom Remote Control 76, 1834–1848 (2015). https://doi.org/10.1134/S0005117915100112

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