Skip to main content
SpringerLink
Log in

Sum Codes with Efficient Detection of Twofold Errors for Organization of Concurrent Error-Detection Systems of Logical Devices

  • Control in Technical Systems
  • Published:
Automation and Remote Control Aims and scope Submit manuscript

Abstract

Developed were new sum codes detecting efficiently twofold errors in the data vectors. A method of constructing concurrent error-detection systems of the logical combination devices with detection of all single malfunctions based on decomposing the outputs into individual groups and checking them with the use of new sum codes was proposed.

This is a preview of subscription content, log in via an institution to check access.

Access this article

Log in via an institution

Price excludes VAT (USA)
Tax calculation will be finalised during checkout.

Instant access to the full article PDF.

Institutional subscriptions

Similar content being viewed by others

References

  1. McCluskey, E.J., Logic Design Principles: With Emphasis on Testable Semicustom Circuits, New Jersey: Prentice Hall, 1986.

    Google Scholar 

  2. Sogomonyan, E.S. and Slabakov, E.V., Samoproveryaemye ustroistva i otkazoustoichivye sistemy (Selftesting Devices and Fault-tolerant Systems), Moscow: Radio i Svyaz’, 1989.

    Google Scholar 

  3. Piestrak, S.J., Design of Self-Testing Checkers for Unidirectional Error Detecting Codes, Wrocław: Oficyna Wydawnicza Politechniki Wrocłavskiej, 1995.

    Google Scholar 

  4. Abramovici, M., Breuer, M.A., and Friedman, A.D., Digital System Testing and Testable Design, New Jersey: IEEE Press, 1998.

    Google Scholar 

  5. Nicolaidis, M. and Zorian, Y., On-Line Testing for VLSI—A Compendium of Approaches, J. Electron. Testing: Theory Appl., 1998, vol. 12, no. 1–2, pp. 7–20.

    Google Scholar 

  6. Ubar, R., Raik, J., and Vierhaus, H.-T., Design and Test Technology for Dependable Systems-on-Chip, Hershey: IGI Global, 2011.

    Book  Google Scholar 

  7. Drozd, A.V., Kharchenko, V.S., Antoshchuk, S.G., et al., Rabochee diagnostirovanie bezopasnykh informatsionno-upravlyayushchikh sistem (Operational Diagnosis of Safe Data Control Systems), Khar’kov: Zhukovskii Nats. Aerokosm. Univ. “KHAI,” 2012.

    Google Scholar 

  8. Kharchenko, V., Kondratenko, Yu., and Kacprzyk, J., Green IT Engineering: Concepts, Models, Complex Systems Architectures, Springer: New York, 2017, vol.74.

  9. Berger, J.M., A Note on Error Detection Codes for Asymmetric Channels, Inform. Control, 1961, vol. 4, no. 1, pp. 68–73.

    Article  MathSciNet  MATH  Google Scholar 

  10. Efanov, D., Sapozhnikov, V., Sapozhnikov, Vl., and Blyudov, A., On the Problem of Selection of Code with Summation for Combinational Circuit Test Organization: in Proc. 11 IEEE East-West Design and Test Sympos. (EWDTS‘2013), Rostov-on-Don, Russia, September 27–30, 2013, pp. 261–266.

    Google Scholar 

  11. Efanov, D.V., Sapozhnikov, V.V., and Sapozhnikov, Vl.V., On Summation Code Properties in Functional Control Circuits, Autom. Remote Control, 2010, vol. 71. no. 6, pp. 1117–1123.

    Article  MathSciNet  MATH  Google Scholar 

  12. Blyudov, A.A., Efanov, D.V., Sapozhnikov, V.V., and Sapozhnikov, Vl.V., Construction of Modified Berger Code with Minimal Number of Undetectable Errors in Data Digts, Electron. Model., 2012, vol. 34, no. 6, pp. 17–29.

    Google Scholar 

  13. Das, D. and Touba, N.A., Weight-Based Codes and Their Application to Concurrent Error Detection of Multilevel Circuits, in Proc. 17 IEEE Test Sympos., USA, California, 1999, pp. 370–376.

    Google Scholar 

  14. Das, D., Touba, N.A., Seuring, M., and Gossel, M., Low Cost Concurrent Error Detection Based on Modulo Weight-Based Codes, in Proc. IEEE 6 Int. On-Line Testing Workshop (IOLTW), Spain, Palma de Mallorca, July 3–5, 2000, pp. 171–176.

    Chapter  Google Scholar 

  15. Sapozhnikov, V., Sapozhnikov, Vl., Efanov, D., and Nikitin, D., Combinational Circuits Checking on the Base of Sum Codes with One Weighted Data Bit, in Proc. 12 IEEE East-West Design and Test Sympos. (EWDTS‘2014), Kyev, Ukraine, September 26–29, 2014, pp. 126–136.

    Google Scholar 

  16. Sapozhnikov, V.V., Sapozhnikov, Vl.V., and Efanov, D.V., Weighted Sum Codes for Organization of Check of Logical Devices, Electron. Model., 2014, vol. 36, no. 1, pp. 59–80.

    Google Scholar 

  17. Efanov, D., Sapozhnikov, V., Sapozhnikov, Vl., and Nikitin, D., Sum Code Formation with Minimum Total Number of Undetectable Errors in Data Vectors, in Proc. 13 IEEE East-West Design and Test Sympos. (EWDTS‘2015), Batumi, Georgia, September 26–29, 2015, pp. 141–148.

    Google Scholar 

  18. Mekhov, V.B., Saposhnikov, V.V., and Saposhnikov, Vl.V., Checking of Combinational Circuits Basing on Modification Sum Codes, Autom. Remote Control, 2008, vol. 69, no. 8, pp. 1411–1422.

    Article  MathSciNet  MATH  Google Scholar 

  19. Sapozhnikov, V.V., Sapozhnikov, Vl.V., Efanov, D.V., and Dmitriev, V.V., New Structures of the Concurrent Error Detection Systems for Logic Circuits, Autom. Remote Control, 2017, vol. 78, no. 2, pp. 300–313.

    Article  MathSciNet  MATH  Google Scholar 

  20. Sapozhnikov, V.V., Sapozhnikov, Vl.V., Efanov, D.V., et al., Organization of Concurrent Error Detection Systems Based on the Modified Codes with Summation of Weighted Transitions, Electron. Model., 2015, vol. 37, no. 6, pp. 49–68.

    MATH  Google Scholar 

  21. Göessel, M., Ocheretny, V., Sogomonyan, E., and Marienfeld, D., New Methods of Concurrent Checking: Edition 1, Dordrecht: Springer Science+Business Media, 2008.

    Google Scholar 

  22. Busaba, F.Y. and Lala, P.K., Self-Checking Combinational Circuit Design for Single and Unidirectional Multibit Errors, J. Electron. Testing: Theory Appl., 1994, no. 1, pp. 19–28.

    Article  Google Scholar 

  23. Saposhnikov, V.V., Saposhnikov, Vl.V., Morosov, A., and Göessel, M., Design of Self-Checking Unidirectional Combinational Circuits with Low Area Overheadin, in Proc. IEEE Int. On-Line Testing Workshop (IOLTW), Biarritz, France, 1996, pp. 56–67.

    Google Scholar 

  24. Morosow, A., Sapozhnikov, V.V., Sapozhnikov, Vl.V., and Göessel, M., Self-Checking Combinational Circuits with Unidirectionally Independent Outputs, VLSI Design., 1998, vol. 5, no. 4, pp. 333–345.

    Article  Google Scholar 

  25. Sapozhnikov, V.V., Sapozhnikov, Vl.V., Efanov, D.V., et al., Organization of Concurrent Error Detection Systems Based on the Modified Codes with Summation of Weighted Transitions, Electron. Model., 2016, vol. 38, no. 1, pp. 87–98.

    Google Scholar 

  26. Jha, N.K. and Vora, M.B., At-Unidirectional Errors-Detecting Systematic Code, Comput. Math. Appl., 1988, vol. 16, no. 9, pp. 705–714.

    Article  MathSciNet  MATH  Google Scholar 

  27. Sapozhnikov, V.V., Sapozhnikov, Vl.V., and Efanov, D.V., Classification of Errors in the Data Vectors of Systematic Codes, Izv. Vyssh. Uchebn. Zaved., Priborostr., 2015, vol. 58, no. 5, pp. 333–343.

    Article  MATH  Google Scholar 

  28. Collection of Digital Design Benchmarks. http://ddd.fit.cvut.cz/prj/Benchmarks/

  29. Sapozhnikov, V., Sapozhnikov, Vl., Efanov, D., and Dmitriev, V., New Sum Code for Effective Detection of Twofold Errors in Data Vectorsin, in Proc. 13 IEEE East-West Design and Test Symposium (EWDTS‘2015), Batumi, Georgia, September 26–29, 2015, pp. 154–159.

    Google Scholar 

  30. Göessel, M., Morozov, A.A., Sapozhnikov, V.V., and Sapozhnikov, Vl.V., Investigation of Combination Self-Testing Devices Having Independent and Monotone Independent Outputs, Autom. Remote Control, 1997, vol. 58, no. 5, pp. 299–309.

    MATH  Google Scholar 

  31. Efanov, D.V., Sapozhnikov, V.V., and Sapozhnikov, Vl.V., Conditions for Detecting a Logical Element Fault in a Combination Device under Concurrent Checking Based on Berger Code, Autom. Remote Control, 2017, vol. 78, no. 5, pp. 892–902.

    Article  MATH  Google Scholar 

Download references

Author information

Authors and Affiliations

  1. Emperor Alexander I St. Petersburg State Transport University, St. Petersburg, Russia

    V. V. Dmitriev, D. V. Efanov, V. V. Sapozhnikov & Vl. V. Sapozhnikov

Authors
  1. V. V. Dmitriev
    View author publications

    You can also search for this author in PubMed Google Scholar

  2. D. V. Efanov
    View author publications

    You can also search for this author in PubMed Google Scholar

  3. V. V. Sapozhnikov
    View author publications

    You can also search for this author in PubMed Google Scholar

  4. Vl. V. Sapozhnikov
    View author publications

    You can also search for this author in PubMed Google Scholar

Corresponding author

Correspondence to V. V. Dmitriev.

Additional information

Original Russian Text © V.V. Dmitriev, D.V. Efanov, V.V. Sapozhnikov, Vl.V. Sapozhnikov, 2018, published in Avtomatika i Telemekhanika, 2018, No. 4, pp. 105–122.

Rights and permissions

Reprints and permissions

About this article

Check for updates. Verify currency and authenticity via CrossMark

Cite this article

Dmitriev, V.V., Efanov, D.V., Sapozhnikov, V.V. et al. Sum Codes with Efficient Detection of Twofold Errors for Organization of Concurrent Error-Detection Systems of Logical Devices. Autom Remote Control 79, 665–678 (2018). https://doi.org/10.1134/S0005117918040082

Download citation

  • Received:

  • Published:

  • Issue Date:

  • DOI: https://doi.org/10.1134/S0005117918040082

Keywords

Search

Navigation