Abstract
We propose new fault-tolerant architectures, which, in contrast to the well-known double and triple modular redundancy architectures, include only one copy of the original circuit. In the new architectures, a signal error detection circuit is used to select the functions to be corrected. The circuit is built on the basis of the Boolean complement method with parity check of calculations. A generalized architecture with Boolean complement based signal correction is presented. This architecture permits one to design the simplest fault-tolerant circuits. Algorithms for designing signal error detection circuits, as well as examples of their application, are given.
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REFERENCES
Sogomonyan, E.S. and Slabakov, E.V., Samoproveryaemye ustroistva i otkazoustoichivye sistemy (Self-Checking Devices and Fault-Tolerant Systems), Moscow: Radio Svyaz’, 1989.
Fujiwara, E., Code Design for Dependable Systems: Theory and Practical Applications, Chichester: John Wiley & Sons, 2006.
Gavrilov, S.V., Gurov, S.I., Zhukova, T.D., et al., Methods to increase fault tolerance of combinational integrated microcircuits by redundancy coding, Comput. Math. Model., 2017, vol. 28, no. 3, pp. 400–406. https://doi.org/10.1007/s10598-017-9372-3
Sapozhnikov, V.V., Sapozhnikov, Vl.V., and Efanov, D.V., Kody Khemminga v sistemakh funktsional’nogo kontrolya logicheskikh ustroistv (Hamming Codes in Functional Control Systems of Logical Devices), St. Petersburg: Nauka, 2018.
Gavrilov, M.A., Ostianu, V.M., and Potekhin, A.I., Reliability of discrete systems, Itogi Nauki Tekh., Ser.: Teor. Veroyatn. Mat. Stat. Teor. Kibern., 1969–1970, pp. 7–104.
Karavai, M.F. and Sogomonyan, E.S., Analysis of reliability characteristics of self-checkable redundant structures, Autom. Remote Control, 1980, vol. 40, no. 8, pp. 1186–1197.
Matsumoto, K., Uehara, M., and Mori, H., Evaluating the fault tolerance of stateful TMR, 13th Int.Conf. Network-Based Inf. Syst. (Takayama, Japan, September 14–16, 2010), pp. 332–336. https://doi.org/10.1109/NBiS.2010.86
Borecký, J., Kohlík, M., Vit, P., and Kubátová, H., Enhanced duplication method with TMR-like masking abilities, Euromicro Conf. Digital Syst. Des. (DSD) (Limassol, Cyprus, August 31–September 2, 2016), pp. 690–693. https://doi.org/10.1109/DSD.2016.91
Krcma, M., Kotasek, Z., and Lojda, J., Triple modular redundancy used in field programmable neural networks, Proc. 15th IEEE East-West Des. & Test Symp. (EWDTS’2017) (Novi Sad, Serbia, September 29–October 2, 2017), pp. 372–377. https://doi.org/10.1109/EWDTS.2017.8110128
Sogomonyan, E.S., Self-correction fault-tolerant systems, Preprint, October 2018.
Dug, M., Krstic, M., and Jokic, D., Implementation and analysis of methods for error detection and correction on FPGA, IFAC-PapersOnLine, 2018, vol. 51, no. 6, pp. 348–353.
Kharchenko, V.S., Models and properties of multialternative fault-tolerant systems, Autom. Remote Control, 1993, vol. 53, no. 12, pp. 1944–1950.
Lysenko, I.V. and Kharchenko, V.S., Potential vitality of multi-layered majorant-reserved systems subject to adverse impulse effects, Autom. Remote Control, 1997, vol. 58, no. 2, pp. 320–327.
Sklyar, V.V. and Kharchenko, V.S., Fault-tolerant computer-aided control systems with multiversion-threshold adaptation: adaptation methods, reliability estimation, and choice of an architecture, Autom. Remote Control, 2002, vol. 63, no. 6, pp. 991–1003. https://doi.org/10.1023/A:1016130108770
Sapozhnikov, V.V., Sapozhnikov, Vl.V., and Efanov, D.V., Signal correction for combinational circuits based on Boolean complement with parity check of computations, Informatika, 2020, vol. 17, no. 2, pp. 71–85. https://doi.org/10.37661/1816-0301-2020-17-2-71-85
Sapozhnikov, V.V., Sapozhnikov, Vl.V., and Efanov, D.V., Fault-tolerant Boolean complement based architecture with parity check of the computations, Avtom. Transp., 2020, vol. 6, no. 3, pp. 377–403. https://doi.org/10.20295/2412-9186-2020-6-3-377-403
Lala, P.K., Self-Checking and Fault-Tolerant Digital Design, San Francisco: Morgan Kaufmann, 2001.
Göessel, M., Morozov, A.V., Sapozhnikov, V.V., and Sapozhnikov, Vl.V., Checking combinational circuits by the method of logic complement, Autom. Remote Control, 2005, vol. 66, no. 8, pp. 1336–1346. https://doi.org/10.1007/s10513-005-0174-2
Göessel, M., Ocheretny, V., Sogomonyan, E., and Marienfeld, D., New Methods of Concurrent Checking: Edition 1 , Dordrecht: Springer Sci.+Bus. Media, 2008.
Das, D.K., Roy, S.S., Dmitiriev, A., Morozov, A., and Gössel, M., Constraint don’t cares for optimizing designs for concurrent checking by 1-out-of-3 codes, Proc. 10th Int. Workshop Boolean Probl. (Freiberg, Germany, September, 2012), pp. 33–40.
Sapozhnikov, V.V., Sapozhnikov, Vl.V., and Efanov, D.V., Construction of self-checking architectures of functional control systems based on constant-weight 2-out-of-4 code, Probl. Upr., 2017, no. 1, pp. 57–64.
Efanov, D.V., Sapozhnikov, V.V., Sapozhnikov, Vl.V., and Pivovarov, D.V., Synthesis of self-checking built-in control circuits based on the method of Boolean complement to constant-weight 2-out-of-4 code, Informatika, 2018, vol. 15, no. 4, pp. 71–85.
Saposhnikov, Vl.V., Dmitriev, A., Göessel, M., and Saposhnikov, V.V., Self-dual parity checking – a new method for on line testing, Proc. 14th IEEE VLSI Test Symp. (Princeton, USA, 1996), pp. 162–168.
Sapozhnikov, V.V., Sapozhnikov, Vl.V., and Göessel, M., Samodvoistvennye diskretnye ustroistva (Self-Dual Discrete Devices), St. Petersburg: Energoatomizdat, 2001.
Efanov, D., Sapozhnikov, V., Sapozhnikov, Vl., Osadchy, G., and Pivovarov, D., Self-dual complement method up to constant-weight codes for arrangement of combinational logical circuits concurrent error-detection systems, Proc. 17th IEEE East-West Des. & Test Symp. (EWDTS’2019) (Batumi, Georgia, September 13–16, 2019), pp. 136–143. https://doi.org/10.1109/EWDTS.2019.8884398
Efanov, D.V., Sapozhnikov, V.V., Sapozhnikov, Vl.V., and Pivovarov, D.V., Method of functional control of combinational circuits based on self-dual complement to constant-weight codes, Elektron. Model., 2020,vol. 42, no. 3, pp. 27–52. https://doi.org/10.15407/emodel.42.03.027
Sapozhnikov, V.V., Sapozhnikov, Vl.V., and Efanov, D.V., Osnovy teorii nadezhnosti i tekhnicheskoi diagnostiki (Fundamentals of the Theory of Reliability and Technical Diagnostics), St. Petersburg: Lan’, 2019.
Aksjonova, G.P., Method of synthesizing built-in monitoring arrangements for automata with memory, Autom. Remote Control, 1973, vol. 34, no. 2, pp. 267–273.
Aksjonova, G.P., Necessary and sufficient conditions for design of completely checkable modulo 2 convolution circuits, Autom. Remote Control, 1980, vol. 40, no. 9, pp. 1362–1369.
Sapozhnikov, V.V., Sapozhnikov, Vl.V., and Efanov, D.V., Kody s summirovaniem dlya sistem tekhnicheskogo diagnostirovaniya. T. 1: Klassicheskie kody Bergera i ikh modifikatsii (Sum Codes for Technical Diagnostics Systems. Vol. 1: Classical Berger Codes and Their Modifications), Moscow: Nauka, 2020.
Sapozhnikov, V.V., Sapozhnikov, Vl.V., and Efanov, D.V., Kody s summirovaniem dlya sistem tekhnicheskogo diagnostirovaniya. T. 2: Vzveshennye kody s summirovaniem (Sum Codes for Technical Diagnostics Systems. Vol. 2: Weighted Sum Codes), Moscow: Nauka, 2021.
Sogomonyan, E.S. and Göessel, M., Design of self-testing and on-line fault detection combinational circuits with weakly independent outputs, J. Electron. Test.: Theory Appl., 1993, vol. 4, no. 4, pp. 267–281. https://doi.org/10.1007/BF00971975
Busaba, F.Y. and Lala, P.K., Self-checking combinational circuit design for single and unidirectional multibit errors, J. Electron. Test.: Theory Appl., 1994, vol. 5, no. 5, pp. 19–28. https://doi.org/10.1007/BF00971960
Morosow A, Saposhnikov, V.V., Saposhnikov, Vl.V., and Göessel, M., Self-checking combinational circuits with unidirectionally independent outputs, VLSI Des., 1998, vol. 5, no. 4, pp. 333–345. https://doi.org/10.1155/1998/20389
Matrosova, A., Levin, I., and Ostanin, S., Survivable self-checking sequential circuits, Proc. 2001 IEEE Int. Symp. Defect Fault Tolerance VLSI Syst. (DFT’2001) (San Francisco, October 24–26, 2001), pp. 395–402.
Sapozhnikov, V., Sapozhnikov, Vl., and Efanov, D., Typical signal correction structures based on duplication with the integrated control circuit, Proc. 18th IEEE East-West Des. & Test Symp. (EWDTS’2020) (Varna, Bulgaria, September 4–7, 2020), pp. 78–87. https://doi.org/10.1109/EWDTS50664.2020.9224649
Efanov, D.V., Sapozhnikov, V.V., and Sapozhnikov, Vl.V., Typical structure of a duplicate error correction scheme with code control with summation of weighted transitions, Electron. Model., 2020, vol. 42,no. 5, pp. 38–50. https://doi.org/10.15407/emodel.42.05.038
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Efanov, D.V., Sapozhnikov, V.V. & Sapozhnikov, V.V. Boolean-Complement Based Fault-Tolerant Electronic Device Architectures. Autom Remote Control 82, 1403–1417 (2021). https://doi.org/10.1134/S0005117921080075
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DOI: https://doi.org/10.1134/S0005117921080075