Abstract
The authors theoretically describe the monotonic increasing relationship between average powers of a CMOS VLSI circuit with and without delay. The power of an ideal circuit without delay, which can be fast computed, has been used as the evaluation criterion for the power of a practical circuit with delay, which needs more computing time, in such fields as fast estimation for the average power and the maximum power, and fast optimization for the low test power. The authors propose a novel simulation approach that uses delay-free power to compact a long input vector pair sequence into a short sequence and then, uses the compacted one to fast simulate the average (or maximum) power for a CMOS circuit. In comparison with the traditional simulation approach that uses an un-compacted input sequence to simulate the average (or maximum) power, experiment results demonstrate that in the field of fast estimation for the average power, the present approach can be 6–10 times faster without significant loss in accuracy (less than 3.5% on average), and in the field of fast estimation for the maximum power, this approach can be 6–8 times faster without significant loss in accuracy (less than 5% on average). In the field of fast optimization for the test power, the authors propose a novel delay-free power optimization approach for the test power. Experiment results demonstrate that, in comparison with the approach of direct optimization and the approach of Hamming distance optimization, this approach is of the highest optimization efficiency because it needs shorter time (16.84%) to obtain a better optimization effect (reducing 35.11% test power).
Similar content being viewed by others
References
Najm, F. N., A survey of power estimation techniques in VLSI circuit, IEEE Transactions on VLSI, 1994, 2(4): 446–455.
Burch, R., Najm, F.N., Yang, P. et al., A Monte Carlo approach for power estimation, IEEE Transactions On VLSI, 1993, 1(1): 63–71.
Chou, T. L., Roy, K., Statistical estimation of sequential circuit activity, in Proc. IEEE/ACM Int. Conf. Computer-Aided Design, San Jose: IEEE Computer Society Press, 1995, 34–37.
Najm, F. N., Transition density: A new measure of activity in digital circuit, IEEE Transactions on CAD, 1993, 12(2): 310–323.
Macii, E., Padram, M., Somenzi, F., High-level power modeling, estimation, and optimization, Proc. of IEEE Design Automation Conf. (DAC97), Anaheim: ACM Incorporation, 1997, 504–511.
Chen Zhanping, Roy, K., A power macro-modeling technique based on power sensitivity, Proc. of IEEE Design Automation Conf. (DAC98), San Francisco: ACM Incorporation, 1998, 678–683.
Marculescu, R., Marculescu, D., Pedram, M., Sequence compaction for power estimation: Theory and practice, IEEE Transactions on CAD, 1999, 18(7): 973–993.
Luo Zuying, Min Yinghua, Yang Shiyuan, A novel approach to fast simulate maximum power dissipation of CMOS combinational circuit, Chinese Journal of Computer Aided Design and Computer Graphics, 2001, 13(7): 577–581.
Davadas, S., Keutzer, K., White, J., Estimation of power dissipation in CMOS combinational circuit using Boolean function manipulations, IEEE Transactions on CAD, 1992, 11(3): 373–383.
Wang, C. Y., Roy, K., Maximum power estimation for CMOS circuit using deterministic and statistical approaches, IEEE Trans. on VLSI, 1998, 6(1): 134–140.
Manich, S., Maximizing the weighted switching activity in combinational CMOS circuit under the variable delay model, Proc. of IEEE European Design & Test Conf., Paris: IEEE Computer Society Press, 1997, 597–602.
Zhao Zhuxing, Min Yinhua, The least upper bound of power dissipation in CMOS circuit, Proceeding of CAD & CG’97, Shenzhen: International Academic Publishers World Publishing Corporation, 1997, 506–511.
Hsiao, M. S., Rudnik, E. M., Patel, J. H., Peak power estimation of VLSI circuit: new peak power measures, IEEE Trans. on VLSI, 2000, 8(4): 435–439.
Wang, S., Gupta, S. K., ATPG for heat dissipation minimization during test application, IEEE Trans. on Computers, 1998, 47(2): 256–262.
Chakravarty, S., Dabholkar, V. P., Two techniques for minimizing power dissipation in scan circuit during test application, Proc. of IEEE Asian Test Symposium, Taibei: IEEE Computer Society Press, 1994, 324–329.
Author information
Authors and Affiliations
Corresponding author
Rights and permissions
About this article
Cite this article
Luo, Z., Min, Y., Yang, S. et al. The monotonic increasing relationship between average powers of CMOS VLSI circuits with and without delay and its applications. Sci China Ser F 45, 401–415 (2002). https://doi.org/10.1360/02yf9035
Received:
Issue Date:
DOI: https://doi.org/10.1360/02yf9035