Abstract
We present the design and a closed-form error analysis of accuracy-configurable multipliers via segmented carry chains. To address this problem, we model the approximate partial-product accumulations as a sequential process. According to a given splitting point of the carry chains, the technique herein discussed allows varying the quality of the accumulations and, consequently, the overall product. Due to these shorter critical paths, such kinds of approximate multipliers can trade-off accuracy for an increased performance whilst exploiting the inherent area savings of sequential over combinatorial approaches. We implemented multiple architectures targeting FPGAs and ASICs with different bit-widths and accuracy configurations to 1) estimate resources, power consumption, and delay, as well as to 2) evaluate those error metrics that belong to the so-called #P-complete class.
Funding source: Deutsche Forschungsgemeinschaft
Award Identifier / Grant number: 450987171
Funding statement: This work has been funded by the Deutsche Forschungsgemeinschaft (DFG, German Research Foundation) – 450987171.
About the authors
Jorge Echavarria received his M. Sc. degree in Computer Science from the National Institute of Astrophysics, Optics, and Electronics, Mexico, in 2014. He is currently a Research Assistant pursuing a Ph.D. at the Chair of Hardware/Software Co-Design at the Friedrich-Alexander-Universität Erlangen-Nürnberg (FAU). His research interests include Approximate Computing, Digital Signal Processing, and Reconfigurable Architectures.
Dr.-Ing. Stefan Wildermann received the Diploma degree and Ph.D. degree (Dr.-Ing.) in computer science from Friedrich-Alexander-Universität Erlangen Nürnberg (FAU), Erlangen, Germany, in 2006 and 2012, respectively. He leads the Reconfigurable Computing Group, CS Department, FAU. Since then he has been a Research Assistant, a Lecturer, and a Group Leader with the Chair of Hardware/Software Co-Design, FAU. His current research interests include reconfigurable computing and system-level design automation for embedded systems.
Prof. Dr. rer. nat. Oliver Keszocze is a Professor of Computer Science at the chair for Hardware-Software-Co-Design at the Friedrich-Alexander-Universität Erlangen-Nürnberg (FAU), Erlangen, Germany. His current research interests include several aspects of logic synthesis with a focus on approximate computing for both, ASIC and FPGA. He has been serving as a TPC member for several conferences, including DATE, ICCAD, and ASP-DAC and is a reviewer for IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems as well as for several other journals.
Dr.-Ing. Faramarz Khosravi received his M. Sc. degree in Computer Engineering from Sharif University of Technology, Iran, in 2011, and his Ph. D. degree (Dr.-Ing.) from Friedrich-Alexander-Universität Erlangen-Nürnberg (FAU), Germany, in 2019. In 2013, he joined the chair of Hardware/Software Co-Design at FAU as a research and teaching assistant. His research interests include dependable embedded systems, uncertainty analysis, and multi-objective optimization.
Dr.-Ing. Andreas Becher received his M. Sc. and Ph. D. degrees in Computer Science from the Friedrich-Alexander-Universität Erlangen-Nürnberg (FAU) in 2014 and 2022, respectively. His research interests include System-on-Chip design, energy efficient data processing using FPGAs, and FPGA acceleration.
Prof. Dr.-Ing. Jürgen Teich (Fellow, IEEE) received the MS degree (Dipl.-Ing.; with honors) from the University of Kaiserslautern, Germany, in 1989 and the Ph. D. degree (Dr.-Ing.; summa cum laude) from the University of Saarland, Saarbrücken, Germany, in 1993. He is with Friedrich-Alexander-Universität Erlangen-Nürnberg (FAU), Germany, where he is directing the chair for Hardware/Software Co-Design since 2003. From 1998 to 2002, he was full professor with the Electrical Engineering and Information Technology Department, University of Paderborn, Germany. His current research focuses on electronic design automation of embedded systems with emphasis on hardware/software co-design, reconfigurable computing and multi-core systems. He has organized various ACM/IEEE conferences/symposia as program chair including CODES+ISSS’07, FPL’08, ASAP’10, and DATE’16. He was the vice general chair of DATE 2018 and the general chair of DATE 2019. He also serves in the editorial board of journals including ACM Transactions on Design Automation of Electronic Systems, ACM Transactions on Embedded Computing Systems, and IEEE Design and Test and has edited two text books on Hardware/Software Co-Design and a Handbook on this topic (Springer). Since 2010, he has been the principal coordinator of the Transregional Research Center 89 “Invasive Computing” funded by the German Research Foundation (DFG). He is a member of the Academia Europaea, the Academy of Europe, the National Academy of Science and Engineering (acatech), and the German Society of Humboldtians.
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