Abstract
A multi-stage dual replica bit-line delay (MDRBD) technique is proposed for reducing access time by suppressing the sense-amplifier enable (SAE) timing variation of low voltage static random-access memory (SRAM) applications. Compared with the traditional technique, this strategy, using statistical theory, reduces the timing variation by using multi-stage ideas, meanwhile doubling the replica bit-line (RBL) capacitance and discharge path simultaneously in each stage. At a supply voltage of 0.6 V, the simulation results show that the standard deviations of the SAE timing and cycle time with the proposed technique are 69.2% and 47.2%, respectively, smaller than that with a conventional RBL delay technique in TSMC 65 nm CMOS technology (Taiwan Semiconductor Manufacturing Company, Taiwan).
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Project supported by the National Natural Science Foundation of China (No. 61474001)
ORCID: Chun-yu PENG, http://orcid.org/0000-0003-2408-5048
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Tan, Sb., Lu, Wj., Peng, Cy. et al. Multi-stage dual replica bit-line delay technique for process-variation-robust timing of low voltage SRAM sense amplifier. Frontiers Inf Technol Electronic Eng 16, 700–706 (2015). https://doi.org/10.1631/FITEE.1400439
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DOI: https://doi.org/10.1631/FITEE.1400439