Abstract
A novel dual-edge implicit pulse-triggered flip-flop with an embedded clock-gating scheme (DIFF-CGS) is proposed, which employs a transmission-gate-logic (TGL) based clock-gating scheme in the pulse generation stage. This scheme conditionally disables the inverter chain when the input data are kept unchanged, so redundant transitions of delayed clock signals and internal nodes of the latch are all eliminated, leading to low power efficiency. Based on SMIC 65 nm technology, extensive post-layout simulation results show that the proposed DIFF-CGS gains an improvement of 41.39% to 56.21% in terms of power consumption, compared with its counterparts at 10% data-switching activity. Also, full-swing operations in both implicit pulse generation and the static latch improve the robustness of the design. Thus, DIFF-CGS is suitable for low-power applications in very-large-scale integration (VLSI) designs with low data-switching activities.
This is a preview of subscription content, log in via an institution to check access.
Similar content being viewed by others
References
Geng, L., Shen, J.Z., Xu, C.Y., 2016. Design of flip-flops with clock-gating and pull-up control scheme for powerconstrained and speed-insensitive applications. IET Comput. Dig. Techn., 10(4): 193–201. http://dx.doi.org/10.1049/iet-cdt.2015.0139
Goh, W.L., Yeo, K.S., Zhang, W., et al., 2007. A novel static dual edge-trigger flip-flop for high-frequency low-power application. IEEE Int. Symp. on Integrated Circuits, p.208–211. http://dx.doi.org/10.1109/ISICIR.2007.4441834
Hwang, Y.T., Lin, J.F., Sheu, M.H., 2012. Low-power pulse-triggered flip-flop design with conditional pulseenhancement scheme. IEEE Trans. VLSI Syst., 20(2): 361–366. http://dx.doi.org/10.1109/TVLSI.2010.2096483
Hyman, R., Ranganathan, N., Bingel, T., et al., 2013. A clock control strategy for peak power and RMS current reduction using path clustering. IEEE Trans. VLSI Syst., 21(2): 259–269. http://dx.doi.org/10.1109/TVLSI.2012.2186989
Judy, D.J., Kanchana Bhaaskaran, V.S., 2012. Energy recovery clock gating scheme and negative edge triggering flip-flop for low power applications. Int. Conf. on Devices, Circuits and Systems, p.140–143. http://dx.doi.org/10.1109/ICDCSyst.2012.6188691
Kawaguchi, H., Takayasu, S., 1998. A reduced clock-swing flip-flop (RCSFF) for 63% power reduction. IEEE J. Sol.-State Circ., 33(5): 807–811. http://dx.doi.org/10.1109/4.668997
Kim, S., Han, I., Paik, S., et al., 2011. Pulser gating: a clock gating of pulsed-latch circuits. Proc. IEEE Asia South Pacific Design Automation Conf., p.190–195. http://dx.doi.org/10.1109/ASPDAC.2011.5722182
Klass, F., Amir, C., Das, A., et al., 1999. A new family of semidynamic and dynamic flip-flops with embedded logic for high-performance processors. IEEE J. Sol.-State Circ., 34(5): 712–716.1 http://dx.doi.org/10.1109/ASPDAC.2011.5722182
Ko, U., Balsara, P.T., 2000. High-performance energyefficient D-flip-flop circuits. IEEE Trans. VLSI Syst., 8(1): 94–98. http://dx.doi.org/10.1109/92.820765
Kong, B.S., Kim, S.S., Jun, Y.H., 2001. Conditional-capture flip-flop for statistical power reduction. IEEE J. Sol.-State Circ., 36(8): 1263–1271. http://dx.doi.org/10.1109/4.938376
Kulkarni, S.H., Sylvester, D., 2004. High performance level conversion for dual VDD design. IEEE Trans. VLSI Syst., 12(9): 926–936. http://dx.doi.org/10.1109/TVLSI.2004.833667
Maxim, A., Gheorghe, M., 2001. A novel physical based model of deep submicron CMOS transistors mismatch for Monte Carlo SPICE simulation. IEEE Int. Symp. on Circuits and Systems, p.511–514. http://dx.doi.org/10.1109/ISCAS.2001.922097
Nedovic, N., Aleksic, M., Oklobdzija, V.G., 2002. Conditional pre-charge techniques for power-efficient dual-edge clocking. Proc. Int. Symp. on Low Power Electronics and Design, p.56–59. http://dx.doi.org/10.1109/LPE.2002.146709
Phyu, M.W., Fu, K., Goh, W.L., et al., 2011. Power-efficient explicit-pulsed dual-edge triggered sense-amplifier flip-flops. IEEE Trans. VLSI Syst., 19(1): 1–9. http://dx.doi.org/10.1109/TVLSI.2009.2029116
Shen, J.Z., Geng, L., Wu, X.X., 2015. Low power pulsetriggered flip-flop based on clock triggering edge control technique. J. Circ. Syst. Comput., 24(07): 1550094. http://dx.doi.org/10.1142/S0218126615500942
Stojanovic, V., Oklobdzija, V.G., 1999. Comparative analysis of master-slave latches and flip-flops for highperformance and low-power systems. IEEE J. Sol.-State Circ., 34(4): 536–548. http://dx.doi.org/10.1109/4.753687
Strollo, A.G.M., de Caro, D., Napoli, E., et al., 2005. A novel high-speed sense-amplifier-based flip-flop. IEEE Trans. VLSI Syst., 13(11): 1266–1274. http://dx.doi.org/10.1109/TVLSI.2005.859586
Teh, C.K., Hamada, M., Fujita, T., et al., 2006. Conditional data mapping flip-flops for low-power and highperformance systems. IEEE Trans. VLSI Syst., 14(12): 1379–1383. http://dx.doi.org/10.1109/TVLSI.2006.887833
Teh, C.K., Fujita, T., Hara, H., et al., 2011. A 77% energysaving 22-transistor single-phase-clocking D-flip-flop with adoptive-coupling configuration in 40nm CMOS. IEEE Int. Solid-State Circuits. Conf. on Digest of Technical Papers, p.338–340. http://dx.doi.org/10.1109/ISSCC.2011.5746344
Weste, N.H.E., 2006. CMOS VLSI Design: a Circuits and Systems Perspective (3rd Ed.). Pearson Education, Noida, India.
Wu, Q., Pedram, M., Wu, X., 2000. Clock-gating and its application to low power design of sequential circuits. IEEE Trans. Circ. Syst., 47(3): 415–420. http://dx.doi.org/10.1109/81.841927
Wu, X.X., Shen, J.Z., 2012. Low-power explicit-pulsed triggered flip-flop with robust output. Electron. Lett., 48(24): 1523–1525. http://dx.doi.org/10.1049/Fel.2012.0943
Xiang, G.P., Shen, J.Z., Wu, X.X., et al., 2013. Design of a low-power pulse-triggered flip-flop with conditional clock technique. IEEE Int. Symp. on Circuits and Systems, p.121–124. http://dx.doi.org/10.1109/ISCAS.2013.6571797
Zeitzoff, P.M., Chung, J.E., 2005. A perspective from the 2003 ITRS: MOSFET scaling trends, challenges, and potential solutions. IEEE Circ. Dev. Mag., 21(1): 4–15. http://dx.doi.org/10.1109/MCD.2005.1388764
Zhao, P., Darwish, T.K., Bayoumi, M.A., 2004. Highperformance and low power conditional discharge flip-flop. IEEE Trans. VLSI Syst., 12(5): 477–484. http://dx.doi.org/10.1109/TVLSI.2004.826192
Author information
Authors and Affiliations
Corresponding author
Additional information
Project supported by the National Natural Science Foundation of China (Nos. 61071062 and 61471314) and the Zhejiang Provincial Natural Science Foundation of China (No. LY13F010001)
ORCID: Ji-zhong SHEN, http://orcid.org/0000-0002-9031-2379
Rights and permissions
About this article
Cite this article
Geng, L., Shen, Jz. & Xu, Cy. Power-efficient dual-edge implicit pulse-triggered flip-flop with an embedded clock-gating scheme. Frontiers Inf Technol Electronic Eng 17, 962–972 (2016). https://doi.org/10.1631/FITEE.1500293
Received:
Accepted:
Published:
Issue Date:
DOI: https://doi.org/10.1631/FITEE.1500293