Skip to main content
Log in

Introducing scalable 1-bit full adders for designing quantum-dot cellular automata arithmetic circuits

用于设计量子点元胞自动机算术电路的可扩展 1 位全加器

  • Research Article
  • Published:
Frontiers of Information Technology & Electronic Engineering Aims and scope Submit manuscript

Abstract

Designing logic circuits using complementary metal-oxide-semiconductor (CMOS) technology at the nano scale has been faced with various challenges recently. Undesirable leakage currents, the short-effect channel, and high energy dissipation are some of the concerns. Quantum-dot cellular automata (QCA) represent an appropriate alternative for possible CMOS replacement in the future because it consumes an insignificant amount of energy compared to the standard CMOS. The key point of designing arithmetic circuits is based on the structure of a 1-bit full adder. A low-complexity full adder block is beneficial for developing various intricate structures. This paper represents scalable 1-bit QCA full adder structures based on cell interaction. Our proposed full adders encompass preference aspects of QCA design, such as a low number of cells used, low latency, and small area occupation. Also, the proposed structures have been expanded to larger circuits, including a 4-bit ripple carry adder (RCA), a 4-bit ripple borrow subtractor (RBS), an add/sub circuit, and a 2-bit array multiplier. All designs were simulated and verified using QCA Designer-E version 2.2. This tool can estimate the energy dissipation as well as evaluate the performance of the circuits. Simulation results showed that the proposed designs are efficient in complexity, area, latency, cost, and energy dissipation.

摘要

近年来, 在纳米尺度上使用互补金属氧化物半导体 (CMOS) 技术设计逻辑电路面临着各种挑战. 漏电流、 短效应沟道和高能量耗散是一些亟待解决的问题. 量子点元胞自动机 (QCA) 代表了未来可能替代CMOS的一种合适选择, 因为与标准CMOS相比, 它消耗的能量微不足道. 设计算术电路关键是基于1位全加器的结构. 低复杂度的全加器模块有利于开发各种复杂结构. 本文介绍了基于单元交互的可扩展1位QCA全加器结构. 我们提出的全加器包含QCA设计偏好, 例如使用的单元数量少、 延迟低和占用面积小. 此外, 所提结构已扩展到更大的电路, 包括4位行波进位加法器 (RCA)、 4位行波借位减法器 (RBS)、 加/减电路和2位阵列乘法器. 所有设计均使用 QCA Designer-E 2.2版软件进行仿真和验证. 该工具可以估计能量消耗以及评估电路的性能. 仿真结果表明, 所提设计在复杂度、 面积、 延迟、 成本和能量消耗方面都是有效的.

This is a preview of subscription content, log in via an institution to check access.

Access this article

Price excludes VAT (USA)
Tax calculation will be finalised during checkout.

Instant access to the full article PDF.

Institutional subscriptions

Similar content being viewed by others

References

Download references

Author information

Authors and Affiliations

Authors

Contributions

Hamideh KHAJEHNASIR-JAHROMI and Pooya TORKZADEH designed the research. Hamideh KHAJEHNASIR-JAHROMI processed the data and drafted the paper. Pooya TORKZADEH helped organize the paper. Pooya TORKZADEH and Massoud DOUSTI revised and finalized the paper.

Corresponding author

Correspondence to Pooya Torkzadeh.

Ethics declarations

Hamideh KHAJEHNASIR-JAHROMI, Pooya TORKZADEH, and Massoud DOUSTI declare that they have no conflict of interest.

Rights and permissions

Reprints and permissions

About this article

Check for updates. Verify currency and authenticity via CrossMark

Cite this article

Khajehnasir-Jahromi, H., Torkzadeh, P. & Dousti, M. Introducing scalable 1-bit full adders for designing quantum-dot cellular automata arithmetic circuits. Front Inform Technol Electron Eng 23, 1264–1276 (2022). https://doi.org/10.1631/FITEE.2100287

Download citation

  • Received:

  • Accepted:

  • Published:

  • Issue Date:

  • DOI: https://doi.org/10.1631/FITEE.2100287

Key words

关键词

CLC number

Navigation