Abstract
The performance of complementary metal oxide semiconductor (CMOS) circuits is affected by electromagnetic interference (EMI), and the study of the circuit’s ability to resist EMI will facilitate the design of circuits with better performance. Current-mode CMOS circuits have been continuously developed in recent years due to their advantages of high speed and low power consumption over conventional circuits under the deep submicron process; their EMI resistance performance deserves further study. This paper introduces three kinds of NOT gate circuits: conventional voltage-mode CMOS, MOS current-mode logic (MCML) with voltage signal of input and output, and current-mode CMOS with current signal of input and output. The effects of EMI on three NOT gate circuits are investigated using Cadence Virtuoso software simulation, and a disturbance level factor is defined to compare the effects of different interference terminals, interference signals’ waveforms, and interference signals’ frequencies on the circuits in the 65 nm process. The relationship between input resistance and circuit EMI resistance performance is investigated by varying the value of cascade resistance at the input of the current-mode CMOS circuits. Simulation results show that the current-mode CMOS circuits have better resistance performance to EMI at high operating frequencies, and the higher the operating frequency of the current-mode CMOS circuits, the better the resistance performance of the circuits to EMI. Additionally, the effects of different temperatures and different processes on the resistance performance of three circuits are also studied. In the temperature range of −40 °C to 125 °C, the higher the temperature, the weaker the resistance ability of voltage-mode CMOS and MCML circuits, and the stronger the resistance ability of current-mode CMOS circuits. In the 28 nm process, the current-mode CMOS circuit interference resistance ability is relatively stronger than that of the other two kinds of circuits. The relative interference resistance ability of voltage-mode CMOS and MCML circuits in the 28 nm process is similar to that of the 65 nm process, while the relative interference resistance ability of current-mode CMOS circuits in the 28 nm process is stronger than that of the 65 nm process. This study provides a basis for the design of current-mode CMOS circuits against EMI.
摘要
电磁干扰会影响CMOS电路工作性能,研究电路抗信号干扰能力将有利于设计性能更优的电路。电流型CMOS电路因在深亚微米工艺下相较于传统电路有高速度、低功耗等优势,近些年得到不断发展,其抗干扰能力值得进一步研究。文中介绍传统电压型CMOS、MOS电流型逻辑电路(MOS Current-Mode Logic,MCML)、电流型CMOS三种结构的非门电路。通过Cadence Virtuoso软件仿真模拟电磁干扰对三种非门电路的影响,并定义一个受干扰程度因子,用来研究比较不同干扰点、不同干扰波形、不同干扰频率在65纳米工艺下对电路的影响。并通过改变电流型CMOS电路输入端串联电阻值,研究干扰信号电阻与电路抗干扰性的关系。仿真结果表明:在高工作频率下,电流型CMOS电路具有更好的抗干扰性,且电流型CMOS电路工作频率越高,电路抗干扰性越强。此外,还研究了不同温度和不同工艺对三种电路抗干扰性能的影响。在 −40 °C至125 °C温度范围内,温度越高,电压型CMOS和MCML型电路抗干扰能力越弱,电流型CMOS电路抗干扰能力越强。28纳米工艺下,电流型CMOS电路比其他两种电路的相对抗干扰能力更强; 28纳米工艺下电压型CMOS和MCML电路的相对抗干扰能力与65纳米工艺下的相对抗干扰能力相似,而28纳米工艺下电流型CMOS电路的相对抗干扰能力比65纳米工艺下的相对抗干扰能力强。论文工作为设计抗电磁干扰的电流型CMOS电路提供依据。
This is a preview of subscription content, log in via an institution to check access.
Data availability
The data that support the findings of this study are available from the corresponding author upon reasonable request.
References
Albertson RT, Arthur J, Rashid MH, 2006. Overview of electromagnetic interference. 38th North American Power Symp, p.263–266. https://doi.org/10.1109/NAPS.2006.360154
Backstrom MG, Lovstrand KG, 2004. Susceptibility of electronic systems to high-power microwaves: summary of test experience. IEEE Trans Electromagn Compat, 46(3): 396–403. https://doi.org/10.1109/TEMC.2004.831814
Choudhary MS, Pudi NSAK, Redouté JM, et al., 2021. A methodology to emulate the effect of EMI in circuit simulators for wireline communication channel. IEEE Lett Electromagn Compat Pract Appl, 3(3):96–100. https://doi.org/10.1109/LEMCPA.2021.3079803
Deutschmann B, Winkler G, 2023. Characterizing the electromagnetic immunity of operational amplifiers based on EMIRR and DPI. Int Symp on Electromagnetic Compatibility-EMC Europe, p.1–4. https://doi.org/10.1109/EMCEurope57790.2023.10274196
Gupta P, Banerjee R, Sharma R, 2021. Low-voltage low-power CMOS-based current-mode implementation of digital logic gates and combinational circuits. J Circ Syst Comput, 30(12):2150212. https://doi.org/10.1142/S0218126621502121
Hassan H, Anis M, Elmasry M, 2005. MOS current mode circuits: analysis, design, and variability. IEEE Trans Very Large Scale Integr (VLSI) Syst, 13(8):885–898. https://doi.org/10.1109/TVLSI.2005.853609
Hu Y, Wang ZY, Chen H, et al., 2023. Research on radar jamming for detection performance. J Phys Conf Ser, 2517: 012015. https://doi.org/10.1088/1742-6596/2517/1/012015
Kim K, Iliadis AA, 2007a. Critical bit errors in CMOS digital inverters due to pulsed electromagnetic interference. Int Conf on Electromagnetics in Advanced Applications, p.217–220. https://doi.org/10.1109/ICEAA.2007.4387276
Kim K, Iliadis AA, 2007b. Critical upsets of CMOS inverters in static operation due to high-power microwave interference. IEEE Trans Electromagn Compat, 49(4):876–885. https://doi.org/10.1109/TEMC.2007.908820
Liang B, Ma K, Ding Z, et al., 2012. The structure design of MOS current mode logic adder. Int Conf on Microwave and Millimeter Wave Technology, p.1–4. https://doi.org/10.1109/ICMMT.2012.6230289
Lin JF, Chen YN, Zhao DY, et al., 2021. Simulation analysis of the influence of electromagnetic pulse power on the performance degradation of CMOS inverter. CIE Int Conf on Radar, p.1959–1962. https://doi.org/10.1109/Radar53847.2021.10028215
Mu J, Jia X, 2021. Simulation and analysis of the influence of artificial interference signal style on wireless security system performance. IEEE 4th Advanced Information Management, Communicates, Electronic and Automation Control Conf, p.2106–2109. https://doi.org/10.1109/IMCEC51613.2021.9482169
Powell T, Sule NH, Hemmady S, et al., 2018. Predictive model for extreme electromagnetic compatibility on CMOS inverters. Int Symp on Electromagnetic Compatibility, p.113–116. https://doi.org/10.1109/EMCEurope.2018.8485019
Radasky WA, Baum CE, Wik MW, 2004. Introduction to the special issue on high-power electromagnetics (HPEM) and intentional electromagnetic interference (IEMI). IEEE Trans Electromagn Compat, 46(3):314–321. https://doi.org/10.1109/TEMC.2004.831899
Razavi B, 2000. Design of Analog CMOS Integrated Circuits. McGraw-Hill Higher Education, Burr Ridge, USA, p.17–18, 599.
Razavi B, 2008. Fundamentals of Microelectronics. John Wiley & Sons Inc, Hoboken, USA, p.282–284.
Redouté JM, Steyaert MSJ, 2010. EMI-resistant CMOS differential input stages. IEEE Trans Circ Syst I Regular Pap, 57(2):323–331. https://doi.org/10.1109/TCSI.2009.2023836
Redouté JM, Richelli A, 2015. A methodological approach to EMI resistant analog integrated circuit design. IEEE Electromagn Compat Mag, 4(2):92–100. https://doi.org/10.1109/MEMC.2015.7204058
Richelli A, 2012. Increasing EMI immunity in novel low-voltage CMOS OpAmps. IEEE Trans Electromagn Compat, 54(4): 947–950. https://doi.org/10.1109/TEMC.2012.2206815
Richelli A, Colalongo L, Kovacs-Vajna ZM, 2003. Increasing the immunity to electromagnetic interferences of CMOS OpAmps. IEEE Trans Reliab, 52(3):349–353. https://doi.org/10.1109/TR.2003.817847
Singh A, 2017. EMI harderend current mirror. IEEE Int Conf on Circuits and Systems, p.431–436. https://doi.org/10.1109/ICCS1.2017.8326037
Wang GJ, Zhang YZ, Zhao Y, et al., 2022. Design of GPR transmitting pulse signal based on FPGA. 41st Chinese Control Conf, p.3070–3074. https://doi.org/10.23919/CCC55666.2022.9902661
Wang HY, Li JY, Li H, et al., 2008. Experimental study and SPICE simulation of CMOS inverters latch-up effects due to high power microwave interference. Prog Electromagn Res, 87:313–330. https://doi.org/10.2528/PIER08100408
Wang HY, Hu B, Zou H, et al., 2017. Circuit modeling and simulation of CMOS circuits latchup induced by microwave pulse injection. Progress in Electromagnetics Research Symp-Fall, p.2988–2992. https://doi.org/10.1109/PIERS-FALL.2017.8293646
Wunsch DC, Bell RR, 1968. Determination of threshold failure levels of semiconductor diodes and transistors due to pulse voltages. IEEE Trans Nucl Sci, 15(6):244–259. https://doi.org/10.1109/TNS.1968.4325054
Yamashina M, Yamada H, 1992. An MOS current mode logic (MCML) circuit for low-power sub-GHz processors. IEICE Trans Electron, E75-C(10):1181–1187.
Yao MQ, Sun X, 2019. He Figure transformation algorithm based on current-type CMOS circuit. 14th IEEE Int Conf on Electronic Measurement & Instruments, p.279–285. https://doi.org/10.1109/ICEMI46757.2019.9101831
Zupan D, Deutschmann B, 2020. Comparison of EMI improved differential input pair structures within an integrated folded cascode operational transconductance amplifier. Austrochip Workshop on Microelectronics, p.47–52. https://doi.org/10.1109/Austrochip51129.2020.9232994
Author information
Authors and Affiliations
Contributions
Fangjun LIU conducted the investigation, experimental validation, data organization, and drafted the original manuscript. Jiaming SHEN assisted with investigation and validation. Jizhong SHEN provided experimental guidance, supervision, paper review, and editing.
Corresponding author
Ethics declarations
All the authors declare that they have no conflict of interest.
Rights and permissions
About this article
Cite this article
Liu, F., Shen, J. & Shen, J. Research on electromagnetic interference resistance performance of three kinds of CMOS inverters. Front Inform Technol Electron Eng 25, 1390–1405 (2024). https://doi.org/10.1631/FITEE.2400264
Received:
Accepted:
Published:
Issue Date:
DOI: https://doi.org/10.1631/FITEE.2400264
Key words
- Voltage-mode complementary metal oxide semiconductor (CMOS)
- MOS current-mode logic (MCML)
- Current-mode CMOS
- Electromagnetic interference (EMI)
- Inverter