Skip to main content
Log in

A novel ternary JK flip-flop using the resonant tunneling diode literal circuit

  • Published:
Journal of Zhejiang University SCIENCE C Aims and scope Submit manuscript

Abstract

A literal circuit with a three-track-output structure is presented based on resonant tunneling diodes (RTDs). It can be transformed conveniently into a single-track-output structure according to the definition and properties of the literal operation. A ternary resonant tunneling JK flip-flop is created based on the RTD literal circuit and the module-3 operation, and the JK flip-flop also has two optional types of output structure. The design of the ternary RTD JK flip-flop is verified by simulation. The RTD literal circuit is the key design component for achieving various types of multi-valued logic (MVL) flip-flops. It can be converted into ternary D and JK flip-flops, and the ternary JK flip-flop can also be converted simply and conveniently into ternary D and ternary T flip-flops when the input signals satisfy certain logical relationships. All these types of flip-flops can be realized using the traditional Karnaugh maps combined with the literal and module-3 operations. This approach offers a novel design method for MVL resonant tunneling flip-flop circuits.

This is a preview of subscription content, log in via an institution to check access.

Access this article

Price excludes VAT (USA)
Tax calculation will be finalised during checkout.

Instant access to the full article PDF.

Similar content being viewed by others

References

  • Berezowski, K.S., Vrudhula, S.B.K., 2005. Automatic Design of Binary and Multiple-Valued Logic Gates on RTD Series. 8th Euromicro Conf. on Digital System Design—Architectures, Methods and Tools, p.139–142. [doi:10. 1109/DSD.2005.21]

  • Berezowski, K.S., Vrudhula, S.B.K., 2007. Multiple-Valued Logic Circuits Design Using Negative Differential Resistance Devices. Proc. 37th Int. Symp. on Multiple-Valued Logic, p.24–30. [doi:10.1109/ISMVL.2007.36]

  • Bhattacharya, M., Kulkarni, S., Gonzalez, A., Mazumder, P., 2000. Prototyping Technique for Large-Scale RTD-CMOS Circuits. IEEE Int. Symp. on Circuits and Systems, p.635–638.

  • Ebata, T., Omae, U., Machida, K., Hoshi, K., Waho, T., 2010. Enhancement of Comparator Operation Speed by Using Negative-Differential-Resistance Devices. Proc. IEEE Int. Symp. on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems, p.3020–3023. [doi:10.1109/ISCAS.2010.5538003]

  • González, A.F., Bhattacharya, M., Kulkarni, S., Mazumder, P., 2001. CMOS implementation of a multiple-valued logic signed-digit full adder based on negative-differential-resistance devices. IEEE J. Sol. State Circ., 36(6):924–932. [doi:10.1109/4.924855]

    Article  Google Scholar 

  • Guo, W.L., 2009. Resonant Tunneling Devices and Their Applications. Science Press, Beijing, China, p.1–46, 232–234, 350–353 (in Chinese).

    Google Scholar 

  • Hang, G.Q., Zhou, X.C., 2011. Novel CMOS Ternary Flip-Flops Using Double Pass-Transistor Logic. Int. Conf. on Electric Information and Control Engineering, p.5978–5981. [doi:10.1109/ICEICE.2011.5778391]

  • Homma, N., Saito, K., Aoki, T., 2012. Formal Design of Multiple-Valued Arithmetic Algorithms over Galois Fields and Its Application to Cryptographic Processor. Proc. IEEE 42nd Int. Symp. on Multiple-Valued Logic, p.110–115. [doi:10.1109/ISMVL.2012.24]

  • Lee, J., Choi, S., Yang, K., 2010. Implementation of a 4:1 Multiplexing Quantum-Effect IC Based on RTD Circuit Topology. 10th IEEE Conf. on Nanotechnology, p.211–213. [doi:10.1109/NANO.2010.5697741]

  • Li, X.B., 2009. Digital monolithic integrated circuits based on RTTs. Micronanoelectr. Technol., 46(1):1–9 (in Chinese).

    MATH  Google Scholar 

  • Liang, D.S., Gan, K.J., Chun, K.Y., 2010. Frequency Divider Design Using the Λ-Type Negative-Differential-Resistance Circuit. Proc. 53rd IEEE Int. Midwest Symp. on Circuits and Systems, p.969–972. [doi:10.1109/MWS CAS.2010.5548795]

  • Lin, M., Sun, Z.Y., Shen, J.Z., 2004. Design of NAND and NOR logic gates based on RTD. Bull. Sci. Technol., 20(5):434–437 (in Chinese).

    Google Scholar 

  • Lin, M., Lü, W.F., Sun, L.L., 2007. Design of ternary NAND and NOR gates based on resonant tunneling devices. J. Semicond., 28(12):1983–1987 (in Chinese).

    Google Scholar 

  • Lin, M., Lü, W.F., Sun, L.L., 2011a. Design of ternary D flip-flop with pre-set and pre-reset functions based on resonant tunneling diode literal circuit. J. Zhejiang Univ.-Sci. C (Comput. & Electron.), 12(6):507–514. [doi:10. 1631/jzus.C1000222]

    Article  Google Scholar 

  • Lin, M., Zhang, H.P., Sun, L.L., 2011b. Testability Design of Multi-valued RTD Circuits. Int. Conf. on Electronics, Communications and Control, p.510–513. [doi:10.1109/ICECC.2011.6067730]

  • Núñez, J., Quintana, J.M., Avedillo, M.J., 2007. Correct DC Operation in RTD-Based Ternary Inverters. Proc. 2nd IEEE Int. Conf. on Nano/Micro Engineered and Molecular Systems, p.860–865. [doi:10.1109/NEMS.2007.352154]

  • Núñez, J., Quintana, J.M., Avedillo, M.J., 2008. Design of RTD-Based NMIN/NMAX Gates. 8th IEEE Conf. on Nanotechnology, p.518–521. [doi:10.1109/NANO.2008.155]

  • Sasao, T., 2012. Multiple-Valued Input Index Generation Functions: Optimization by Linear Transformation. Proc. IEEE 42nd Int. Symp. on Multiple-Valued Logic, p.185–190. [doi:10.1109/ISMVL.2012.21]

  • Suzuki, S., Hinata, K., Shiraishi, M., Asada, M., Sugiyama, H., Yokoyama, H., 2010. RTD Oscillators at 430–460 GHz with High Output Power (∼200 μW) Using Integrated Offset Slot Antennas. Int. Conf. on Indium Phosphide and Related Materials, p.152–155. [doi:10.1109/ICIPRM.2010.5516019]

  • Uemura, T., Baba, T., 2000. Demonstration of a Novel Multiple-Valued T-Gate Using Multiple-Junction Surface Tunnel Transistors and Its Application to Three-Valued Data Flip-Flop. Proc. 30th IEEE Int. Symp. on Multiple-Valued Logic, p.305–310. [doi:10.1109/ISMVL.2000.848636]

  • Wu, H.X., Zhong, S.N., Cai, Q.L., Xia, Q.B., Chen, Y.Y., 2012. Design of quaternary logic circuits based on multiple-valued current mode. Lect. Notes Electr. Eng., 138:479–488. [doi:10.1007/978-1-4471-2467-2_56]

    Article  Google Scholar 

  • Wu, X.W., 1994. The Design Theory of Multiple Logic Circuits. Hangzhou University Press, Hangzhou, China, p.18–43, 233–261 (in Chinese).

    Google Scholar 

  • Wu, X.W., Bi, D.X., 1984. Research of the ternary flip-flop based on the module algebra. Acta Electron. Sin., 12(3):6–13 (in Chinese).

    Google Scholar 

  • Yuminaka, Y., Okui, M., 2012. Efficient Data Transmission Using Multiple-Valued Pulse-Position Modulation. Proc. IEEE 42nd Int. Symp. on Multiple-Valued Logic, p.7–12. [doi:10.1109/ISMVL.2012.56]

  • Zhang, W.C., Wu, N.J., 2008. Compact voltage-mode multi-valued literal gate using nanoscale ballistic MOSFETs. Electron. Lett., 44(16):968–969. [doi:10.1049/el:20080507]

    Article  Google Scholar 

Download references

Author information

Authors and Affiliations

Authors

Corresponding author

Correspondence to Mi Lin.

Rights and permissions

Reprints and permissions

About this article

Cite this article

Lin, M., Sun, Ll. A novel ternary JK flip-flop using the resonant tunneling diode literal circuit. J. Zhejiang Univ. - Sci. C 13, 944–950 (2012). https://doi.org/10.1631/jzus.C1200214

Download citation

  • Received:

  • Accepted:

  • Published:

  • Issue Date:

  • DOI: https://doi.org/10.1631/jzus.C1200214

Key words

CLC number

Navigation