Abstract
Context-based adaptive binary arithmetic coding (CABAC) is the major entropy-coding algorithm employed in H.264/AVC. In this paper, we present a new VLSI architecture design for an H.264/AVC CABAC decoder, which optimizes both decode decision and decode bypass engines for high throughput, and improves context model allocation for efficient external memory access. Based on the fact that the most possible symbol (MPS) branch is much simpler than the least possible symbol (LPS) branch, a newly organized decode decision engine consisting of two serially concatenated MPS branches and one LPS branch is proposed to achieve better parallelism at lower timing path cost. A look-ahead context index (ctxIdx) calculation mechanism is designed to provide the context model for the second MPS branch. A head-zero detector is proposed to improve the performance of the decode bypass engine according to UEGk encoding features. In addition, to lower the frequency of memory access, we reorganize the context models in external memory and use three circular buffers to cache the context models, neighboring information, and bit stream, respectively. A pre-fetching mechanism with a prediction scheme is adopted to load the corresponding content to a circular buffer to hide external memory latency. Experimental results show that our design can operate at 250 MHz with a 20.71k gate count in SMIC18 silicon technology, and that it achieves an average data decoding rate of 1.5 bins/cycle.
This is a preview of subscription content, log in via an institution to check access.
Similar content being viewed by others
References
Chang, K.H., Lin, Y.L., 2009. A Very High Throughput Fully Hardwired CABAC Decoder. Int. Symp. on Intelligent Signal Processing and Communication Systems, p.200–203. [doi:10.1109/ISPACS.2009.5383868]
Chen, J.W., Lin, Y.L., 2007. A High-Performance Hardwired CABAC Decoder. IEEE Int. Conf. on Acoustics, Speech and Signal Processing, p.37–40. [doi:10.1109/ICASSP.2007.366166]
ITU-T Recommendation H.264:2003. Advanced Video Coding for Generic Audiovisual Services. Telecommunication Standardization Sector of International Telecommunication Union.
Kuo, M.Y., Li, Y., Lee, C.Y., 2011. An Area-Efficient High-Accuracy Prediction-Based CABAC Decoder Architecture for H.264/AVC. IEEE Int. Symp. on Circuit and Systems, p.160–163. [doi:10.1109/ISCAS.2011.5937974]
Li, C.S., Huang, K., Yan, X.L., Feng, J., Ma, D., Ge, H.T., 2010. A High Efficient Memory Architecture for H.264/AVC Motion Compensation. IEEE Int. Conf. on Application-Specific Architecture and Processors, p.239–245. [doi:10.1109/ASAP.2010.5540963]
Li, C.S., Huang, K., Xiu, S.W., Ma, D., Ge, H.T., Yan, X.L., 2011. High efficient pipeline design and implementation for sub-pixel interpolation process in H.264/AVC. J. Zhejiang Univ. (Eng. Sci.), 45(7):1187–1193 (in Chinese). [doi:10.3785/j.issn.1008-973X.2011.07.008]
Liao, Y.H., Li, G.L., Chang, T.S., 2012. A highly efficient VLSI architecture for H.264/AVC level 5.1 CABAC decoder. IEEE Trans. Circ. Syst. Video Technol., 22(2): 272–281. [doi:10.1109/TCSVT.2011.2160752]
Ma, D., Huang, K., Chen, H.F., Yu, M., Yan, X.L., 2011. Mixed increasing filter pipeline design for H.264/AVC deblocking filter. J. Zhejiang Univ. (Eng. Sci.), 45(7): 1206–1214 (in Chinese). [doi:10.3785/j.issn.1008-973X. 2011.07.011]
Shi, B., Zheng, W., Lee, H.S., Li, D.X., Zhang, M., 2008. Pipelined Architecture Design of H.264/AVC CABAC Real-Time Decoding. 4th IEEE Int. Conf. on Circuits and Systems for Communications, p.492–496. [doi:10.1109/ICCSC.2008.110]
Xu, K., Choy, C.S., Chan, C.F., Pun, K.P., 2006. Power-Efficient VLSI Implementation of Bit Stream Parsing in H.264/AVC Decoder. IEEE Int. Symp. on Circuit and Systems, p.984–988. [doi:10.1109/ISCAS.2006.1693839]
Yang, Y.C., Guo, J.I., 2009. High-throughput H.264/AVC high-profile CABAC decoder for HDTV applications. IEEE Trans. Circ. Syst. Video Technol., 19(9):1395–1399. [doi:10.1109/TCSVT.2009.2020340]
Yang, Y.C., Lin, C.C., Chang, H.C., Su, C.L., Guo, J.I., 2006. A High Throughput VLSI Architecture Design for H.264 Context-Based Adaptive Binary Arithmetic Decoding with Look Ahead Parsing. IEEE Int. Conf. on Multimedia and Expo, p.357–360. [doi:10.1109/ICME.2006.262510]
Yu, W., He, Y., 2005. A high performance CABAC decoding architecture. IEEE Trans. Consum. Electron., 51(4): 1352–1359. [doi:10.1109/TCE.2005.1561867]
Yuan, T.C., 2008. A Novel Pipeline Architecture for H.264/AVC CABAC Decoder. IEEE Asia Pacific Conf. on Circuit and Systems, p.208–311. [doi:10.1109/APCCAS.2008.4746021]
Author information
Authors and Affiliations
Corresponding author
Additional information
Project supported by the National Natural Science Foundation of China (No. 61100074) and the Fundamental Research Funds for the Central Universities, China (No. 2013QNA5008)
Rights and permissions
About this article
Cite this article
Huang, K., Ma, D., Yan, Rj. et al. High throughput VLSI architecture for H.264/AVC context-based adaptive binary arithmetic coding (CABAC) decoding. J. Zhejiang Univ. - Sci. C 14, 449–463 (2013). https://doi.org/10.1631/jzus.C1200250
Received:
Accepted:
Published:
Issue Date:
DOI: https://doi.org/10.1631/jzus.C1200250