Abstract
High-speed, fixed-latency serial links find application in distributed data acquisition and control systems, such as the timing trigger and control (TTC) system for high energy physics experiments. However, most high-speed serial transceivers do not keep the same chip latency after each power-up or reset, as there is no deterministic phase relationship between the transmitted and received clocks after each power-up. In this paper, we propose a fixed-latency serial link based on high-speed transceivers embedded in Xilinx field programmable gate arrays (FPGAs). First, we modify the configuration and clock distribution of the transceiver to eliminate the phase difference between the clock domains in the transmitter/receiver. Second, we use the internal alignment circuit of the transceiver and a digital clock manager (DCM)/phase-locked loop (PLL) based clock generator to eliminate the phase difference between the clock domains in the transmitter and receiver. The test results of the link latency are shown. Compared with existing solutions, our design not only implements fixed chip latency, but also reduces the average system lock time.
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Project supported by the National Science and Technology Support Program of China (No. 2012BAK24B01), the Fundamental Research Funds for the Central Universities, China (No. N100204001), the Specialized Research Fund for the Doctoral Program of Higher Education, China (No. 20110042110021), and the National Science Foundation for Post-doctoral Scientists of China (No. 2013M541243)
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Liu, X., Deng, Qx., Hou, Bn. et al. High-speed, fixed-latency serial links with Xilinx FPGAs. J. Zhejiang Univ. - Sci. C 15, 153–160 (2014). https://doi.org/10.1631/jzus.C1300249
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DOI: https://doi.org/10.1631/jzus.C1300249