Abstract
The present article considers the problem of describing models of functional faults of random-access memory devices by means of the VHDL language. A technique of injecting models of faults in random-access memory in the design descriptions of digital devices in the VHDL language is proposed. It is shown that the proposed technique may be applied for evaluating the behavior of a digital device when there are defects present, as well as for verification of testing algorithms for random-access memory devices.
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References
Hwang, E.O., Digital Logic and Microprocessor Design with VHDL, Brooks/Cole, 2005.
Biblio, P.N., Sintez logicheskikh skhem s ispol’zovaniem yazyka VHDL (Synthesis of Logic Circuits using the VHDL Language), SOLON-R, 2002.
Rajsuman, R., System-on-a-Chip. Design and Test, Boston: Artech House Publishers, 2000.
Lala, P.K., Digital Circuits Testing and Testability, New York: Academic, 1997.
Stroud, Charles A., A Designer’s Guide to Built-in Self-Test, Boston: Kluwer Academic Publishers, 2002.
Yarmolik, V.N. and Ivanyuk, A.A., Injection of Functional Faults into VHDL Descriptions of Digital Devices, Avtom. Vychisl. Tekh. (Riga), 2007, no. 3, pp. 3–12 [Autom. Control Comput. Sci., no. 3].
Youngmin, H. and Szygenda, S.A., Design Error Simulation Based on Error Modeling and Sampling Techniques, Math. Comput. in Simulation, 1998, vol. 46, no. 11, pp. 35–46.
Zolotorevich, L.A., Modeling of VLSI Faults at the Behavioral Level in the VHDL Language, Informatika, 2005, no. 3, pp. 135–144.
Jenn, E., Arlat, J., Rimen, M., Ohlsson, J., and Karlsson, J., Fault Injection into VHDL Models: The MEFISTO Tool, Proc. 24th Intern. Symp. Fault Tolerant Computing (Austin, Texas), 1994, pp. 66–75.
Sieh, V., Tschache, O., and Balbach, F., VERIFY: Evaluation of Reliability Using VHDL-Models with Embedded Fault Descriptions, Proc. 27th Intern. Symp. Fault Tolerant Computing (Seattle, Washington), 1997, pp. 32–36.
Ivanyuk, A.A., Simulation of Functional Faults in Digital Devices by means of the VHDL Language, Informatika, 2007, no. 1, pp. 30–40.
Zolotorevich, L.A., Simulation of Faults in VLSI Structures in the VHDL Language, Informatika, 2005, no, 1, pp. 89–94.
Ivanyuk, A.A. and Yarmolik, V.N., Proektirovanie kontroleprigodnykh tsifrovykh ustroistv: monograf (Design of Testable Digital Devices: A Monograph), Minsk: Bestprint, 2006.
Yarmolik, V.N., Ed., Nerazrushayushchee testirovanie zapominayushcikh ustroistv (Nondestructive Testing of Storage Devices), Minsk: Bestprint, 2005.
Van de Goor, A.J., Testing Semiconductor Memories: Theory and Practice, New York: John Wiley & Sons, 1991.
Van de Goor, A.J. and Al-Ars, Z., Functional Memory Faults: A Formal Notation and a Taxonomy, VTS 2000. 18th IEEE VLSI Test Symposium, 2000, pp. 281–289.
Van de Goor, A.J. and Offer man, A., Towards a Uniform Notation for Memory Tests, Proc. Europ. Design and Test Conf., Paris, 1996, p. 420.
ISE WebPACK 9.1i [Electronic Resource], 2008; mode of access: http://www.xilinx.com
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Original Russian Text © A.A. Ivaniuk, A.V. Stepanov, 2008, published in Avtomatika i Vychislitel’naya Tekhnika, 2008, No. 3, pp. 49–58.
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Ivaniuk, A.A., Stepanov, A.V. Injection of functional faults into VHDL descriptions of random-access memory devices. Aut. Conrol Comp. Sci. 42, 145–152 (2008). https://doi.org/10.3103/S0146411608030061
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DOI: https://doi.org/10.3103/S0146411608030061