Abstract
To verify real-time properties of UML statecharts one may apply a UPPAAL, toolbox for model checking of real-time systems. One of the most suitable ways to specify an operational semantics of UML statecharts is to invoke the formal model of Hierarchical Timed Automata. Since the model language of UPPAAL is based on Networks of Timed Automata one has to provide a conversion of Hierarchical Timed Automata to Networks of Timed Automata. In this paper we describe this conversion algorithm and prove that it is correct w.r.t. UPPAAL query language which is based on the subset of Timed CTL.
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References
David, A. and Moller, M.O., From HUppaal to Uppaal: a translation from hierarchical timed automata to flat timed automata, Research Series RS-01-11, BRICS, Department of Computer Science, University of Aarhus, 2001.
Lakhnech, M.E. and Siegal, M., Hierarchical automata as model for statechart, Lecture Notes Compt. Sci., 1997, vol. 1345, pp. 187–196.
Chen Hai-yan, Dong Wei, and Wang Huo-wang, Verify UML statechart with SMV, Wuhan Univ. J. Natur. Sci., 2001, vol. 6, pp. 183–190.
Jussila, J., Dubrovin, T., Junttila, T., and Latvala, I., Pores. Model checking dynamic and hierarchical UML state machines, Proc. 3rd Workshop on Model Design and Validation, 2006.
Latella, D., Majzik, I., and Massink, M., Automatic verification of a behavioral subset of UML statechart diagrams using SPIN model-checker, Formal Aspects Compt., 1999, vol. 11á pp. 637–664.
Lilius, J. and Paltor, I., vUML: A Tool for Verifying UML Models Technical Report TUCS-272. Turku Centre for Computer Science, 1999.
Ober, I., Graf, S., and Ober, I., Validating timed UML models by simulation and verification, Proc. Workshop on Specification and Validation of UML Models for Real Time and Embedded Systems, 2003.
Behrmann, G., David, A., and Larsen, K.G., A tutorial on Uppaal, Lecture Notes in Compt. Sci., 2004, vol. 3185, pp. 200–236.
Bengtsson, G., Larsen, K.G., Larsson, F., Pettersson, P., and Yi, W., UPPAAL — a tool suite for automatic verification of real-time systems, Lecture Notes in Compt. Sci., 1996, vol. 1066, pp. 232–243.
David, A., Moller, M.O., and Yi, W., Verification of UML Statechart with Real-Time Extensions IT Tech. Rep. 2003-009, Uppsala: Dep. of Information Technology, Uppsala University. 2003.
Muniz, A.L.N., Andrade, A.M.S., and Lima, G., Integrating UML and UPPAAL for designing, specifying and verifying component-based real-time systems, in Innovation in Software and System Engineering, 2009.
Alur, R. and Dill, D.L., Automata for modeling real-time systems, Lecture Notes in Compt. Sci., 1990, vol. 443, pp. 322–335.
Alur, R. and Dill, D.L., A theory of timed automata. Theor. Compt. Sci., 1994, vol. 126, pp. 183–235.
Browne, M.C., Clarke, M.C., and Grumberg, O., Characterizing finite Kripke structures in propositional temporal logics, Theor. Compt. Sci., 1988, vol. 59, pp. 115–131.
Chistolinov, M.V., Epatko, I.V., Bahmurov, A.G., Smelyansky, R.L., Zakharov, V.A., Winter, K., and Usenko, Y., Towards a unified toolset for embedded systems development, Proc. Conf. UKRPROG-2000. Problems of Programming, 2000, nos.1–2, pp. 316–322.
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Konnov, I.V., Podymov, V.V., Volkanov, D.Y. et al. How to make a simple tool for verification of real-time systems. Aut. Control Comp. Sci. 48, 534–542 (2014). https://doi.org/10.3103/S0146411614070232
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DOI: https://doi.org/10.3103/S0146411614070232