Designing Algorithms for the EMU Migrating-threads-based Architecture
The decades-old memory bottleneck problem for data-intensive applications is getting worse as the processor core counts continue to increase. Workloads with sparse memory access characteristics only achieve a fraction of a system’s total memory bandwidth. EMU architecture provides a radical approach to the issue by migrating the computational threads to the location where the data resides. The system enables access to a large PGAS-type memory for hundreds of nodes via a Cilk- based multi-threaded execution scheme.EMU architecture brings brand new challenges in application design and development. Data distribution and thread creation strategies play a crucial role in achieving optimal performance in the EMU platform. In this work, we identify several design considerations that need to be taken care of while developing applications for the new architecture and we evaluate their performance effects on the EMU-chick hardware. We also present a modified BFS algorithm for the EMU system and give experi- mental results for its execution on the platform.
- Research Organization:
- Oak Ridge National Lab. (ORNL), Oak Ridge, TN (United States)
- Sponsoring Organization:
- USDOE
- DOE Contract Number:
- AC05-00OR22725
- OSTI ID:
- 1474509
- Resource Relation:
- Conference: 2018 IEEE High Performance Extreme Computing Conference - Waltham, Massachusetts, United States of America - 9/25/2018 4:00:00 AM-9/27/2018 4:00:00 AM
- Country of Publication:
- United States
- Language:
- English
Similar Records
Programming Strategies for Irregular Algorithms on the Emu Chick
Exploring Hardware Support For Scaling Irregular Applications on Multi-node Multi-core Architectures