N. Vijaykrishnan
M. J. Irwin
Abstract
With the emergence of a plethora of embedded and portable applications, energy dissipation has joined throughput, area, and accuracy/precision as a major design constraint. Thus, designers must be concerned with both optimizing and estimating the energy consumption of circuits, architectures, and software. Most of the research in energy optimization and/or estimation has focused on single components of the system and has not looked across the interacting spectrum of the hardware and software. The novelty of our new energy estimation framework, SimplePower, is that it evaluates the energy considering the system as a whole rather than just as a sum of parts, and that it concurrently supports both compiler and architectural experimentation.
We present the design and use of the SimplePower framework that includes a transition-sensitive, cycle-accurate datapath energy model that interfaces with analytical and transition sensitive energy models for the memory and bus subsystems, respectively. We analyzed the energy consumption of ten codes from the multidimensional array domain, a domain that is important for embedded video and signal processing systems, after applying different compiler and architectural optimizations. Our experiments demonstrate that early estimates from the SimplePower energy estimation framework can help identify the system energy hotspots and enable architects and compiler designers to focus their efforts on these areas.
- 1 B. Ackland and C. Nicol. High performance DSPs - what's hot and what's not? In Proceedings of International Symposium on Low Power Electronics and Design, pages 1-6, August 1998. Google Scholar
Digital Library
- 2 D. Blaauw, A. Dharchoudhury, R. Panda, S. Sirichottiyakul, C. Oh, and T. Edwards. Emerging power management tools for processor design. In Proceedings of International Symposium on Low Power Electronics and Design, pages 143-148, August 1998. Google ScholarDigital Library
- 3 D. Burger and T. Austin. The simplescalar tool set, version 2.0. Technical report, Computer Sciences Department, University of Wisconsin, June, 1997.Google Scholar
- 4 B. Calder, D. Grunwald, and J. Emer. Predictive sequential associative cache. In Proceedings of Second International Symposium on High-Performance Computer Architecture, pages 244-253, 1996. Google ScholarDigital Library
- 5 S. Carr and Y. Guan. Unroll-and-jam using uniformly generated sets. In Proceedings of the 30th International Symposium on Microarchitecture, Research Triangle Park, NC, December 1997. Google ScholarDigital Library
- 6 F. Catthoor, S. Wuytack, E. D. Greef, F. Balasa, L. Nachtergaele, and A. Vandecappelle. Custom memory management methodology - exploration of memory organization for embedded multimedia system design. Kluwer Academic Publishers, June 1998. Google ScholarDigital Library
- 7 A. Chandrakasan and R. Brodersen. Low Power Digital CMOS Design. Kluwer Academic Publishers, 1995. Google ScholarDigital Library
- 8 R. Chen, N. Vijaykrishnan, and M. J. Irwin. Clock power issues in system-on-chip designs. In Proceedings of the Annual IEEE CS Workshop on VLSI, pages 48-53, 1999. Google ScholarDigital Library
- 9 R. Y. Chen, R. M. Owens, and M. J. Irwin. Validation of an architectural level power analysis technique. In Proceedings of the Design Automation Conference, page 242, June 1998. Google ScholarDigital Library
- 10 K. Inoue, T.Ishihara, and K. Murakami. Way-predicting set-associative cache for high performance and low energy consumption. In Proceedings of the International Symposium on Low Power Electronics and Design, pages 273-275, 1999. Google ScholarDigital Library
- 11 M. J. Irwin and N. Vijaykrishnan. Energy issues in multimedia systems. In Proceedings of Workshop on Signal Processing Systems, pages 24-33, October 1999.Google ScholarCross Ref
- 12 K. Itoh, K. Sasaki, and Y. Nakagome. Trends in low-power ram circuit technologies. Proceedings of IEEE, pages 524 -543, Vol. 83. No. 4, April 1995.Google Scholar
- 13 M. Kamble and K. Ghose. Analytical energy dissipation models for low power caches. In Proceedings of International Symposium on Low Power Electronics and Design, page 143, August 1997. Google ScholarDigital Library
- 14 M. Kandemir, A. Choudhary, J. Ramanujam, and P. Banerjee. Improving locality using loop and data transformations in an integrated framework. In Proceedings of the 31st International Symposium on Microarchitecture, pages 285-296, December, 1998. Google ScholarDigital Library
- 15 R. R. Kessler, R. Jooss, A. Lebeck, and M. D. Hill. Inexpensive implementations of self-associativity. In 16th Annual International Symposium on Computer Architecture, 1989. Google ScholarDigital Library
- 16 J. Kin, G. M. Gupta, and W. H. Mangione-Smith. The filter cache : an energy efficient memory structure. In Proceedings of the 30th Annual International Symposium on Microarchitecture, pages 184-193, 1997. Google ScholarDigital Library
- 17 Y. Li and J. Henkel. A framework for estimating and minimizing energy dissipation of embedded hw/sw systems. In Proceedings of the Design Automation Conference, pages 188-191, 1998. Google ScholarDigital Library
- 18 S. Y. Liao. Code Generation and Optimization for Embedded Digital Signal Processors. PhD thesis, Dept. of EECS, MIT, Cambridge, Massachusetts, June 1996. Google ScholarDigital Library
- 19 D. Liu and C. Svensson. Power consumption estimation in cmos vlsi chips. IEEE Journal of Solid-State Circuits, page 663, June 1994.Google Scholar
- 20 H. Mehta, R. M. Owens, and M. J. Irwin. Energy characterization based on clustering. In Proceedings of the Design Automation Conference, page 702, June 1996. Google ScholarDigital Library
- 21 S. S. Muchnick. Advanced Compiler Design Implementation. Morgan Kaufmann Publishers, San Francisco, California, 1997. Google ScholarDigital Library
- 22 Y. Nunomura and et.al. M32R/D-Integrating DRAM and microprocessor. In IEEE MICRO, November/December 1997. Google ScholarDigital Library
- 23 K. Roy and M. C. Johnson. Software design for low power. NATO Advanced Study Institute on Low Power Design in Deep Sub-micron Electronics, August 1996. Google ScholarDigital Library
- 24 W.-T. Shiue and C. Chakrabarti. Memory exploration for low power, embedded systems, CLPE-TR-9-1999-20. Technical report, Arizona State University, 1999.Google Scholar
- 25 C. L. Su and A. M. Despain. Cache designs for energy efficiency. In Proceedings of the 28th Hawaii International Conference on System Sciences, January 1995. Google ScholarDigital Library
- 26 V. Tiwari, S. Malik, A. Wolfe, and T. Lee. Instruction level power analysis and optimization of software. Journal of VLSI Signal Processing Systems, Vol. 13, No. 2, August 1996. Google ScholarDigital Library
- 27 M. Wolf, D. Maydan, and D. Chen. Combining loop transformations considering caches and scheduling. In Proceedings of the Annual International Symposium on Microarchitecture, page 274, December 1996. Google ScholarDigital Library
- 28 M. Wolfe. High Performance Compilers for Parallel Computing. Addison-Wesley Publishing Company, 1996. Google ScholarDigital Library
Index Terms
- Energy-driven integrated hardware-software optimizations using SimplePower
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