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A visual approach to validating system level designs

Published: 02 October 2002 Publication History

Abstract

This paper proposes a simulation-based methodology for validation of a system under design in an early phase of development. The key element of this approach is the visual specification, as Live Sequence Charts (LSCs), of the properties to be checked. The LSCs are automatically translated into the input format for the SystemC-based checker engine, which indicates during simulation, if the property is fulfilled or produces a counter-example, if the property is violated. The entire process from the visual property specification to the checking is largely automated, which makes our approach accessible even for users which have not been trained in formal methods.

References

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W.Damm and D.Harel. LSCs: Brea hing Life into Message Sequence Charts. Formal Methods in System Design 19(1): 45--80, July 2001.
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K.Fisler. Timing Diagrams: Formalization and Formal Verification. Journal of Logic, Language and Information 8(3),1999.
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Cited By

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  • (2005)From Live Sequence Charts to State Machines and BackIEEE Transactions on Software Engineering10.1109/TSE.2005.13731:12(999-1014)Online publication date: 1-Dec-2005
  • (2005)Symbolic Model Checking and Simulation with Temporal AssertionsAdvances in Design and Specification Languages for SoCs10.1007/0-387-26151-6_20(275-291)Online publication date: 2005
  • (2004)Modeling and Formal Verification of Production Automation SystemsIntegration of Software Specification Techniques for Applications in Engineering10.1007/978-3-540-27863-4_29(541-566)Online publication date: 2004
  • Show More Cited By

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cover image ACM Conferences
ISSS '02: Proceedings of the 15th international symposium on System Synthesis
October 2002
278 pages
ISBN:1581135769
DOI:10.1145/581199
Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Association for Computing Machinery

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Publication History

Published: 02 October 2002

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Author Tags

  1. sequence charts
  2. simulation
  3. validation methodology

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ISSS '02 Paper Acceptance Rate 38 of 71 submissions, 54%;
Overall Acceptance Rate 38 of 71 submissions, 54%

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Cited By

View all
  • (2005)From Live Sequence Charts to State Machines and BackIEEE Transactions on Software Engineering10.1109/TSE.2005.13731:12(999-1014)Online publication date: 1-Dec-2005
  • (2005)Symbolic Model Checking and Simulation with Temporal AssertionsAdvances in Design and Specification Languages for SoCs10.1007/0-387-26151-6_20(275-291)Online publication date: 2005
  • (2004)Modeling and Formal Verification of Production Automation SystemsIntegration of Software Specification Techniques for Applications in Engineering10.1007/978-3-540-27863-4_29(541-566)Online publication date: 2004
  • (2004)Formal Verification of LSCs in the Development ProcessIntegration of Software Specification Techniques for Applications in Engineering10.1007/978-3-540-27863-4_27(494-516)Online publication date: 2004

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