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Title: Increased stuck-at fault coverage with reduced I sub DDQ test sets

Conference ·
; ;  [1];  [2]
  1. Sandia National Labs., Albuquerque, NM (USA)
  2. New Mexico Univ., Albuquerque, NM (USA). Dept. of Electrical and Computer Engineering
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Simplified ATPG and fault simulation algorithms, reduced test set sizes, and increased fault coverage are achieved with I {sub DDQ} testing for stuck-at faults. In addition, I {sub DDQ} testing will detect logically redundant and multiple stuck-at faults, and improve the detection of non-stuck-at fault defects. 17 refs., 6 figs., 6 tabs.

Research Organization:
New Mexico Univ., Albuquerque, NM (USA). Dept. of Electrical and Computer Engineering
Sponsoring Organization:
DOE/DP
DOE Contract Number:
AC04-76DP00789
OSTI ID:
7202990
Report Number(s):
SAND-90-0608C; CONF-9005158-1; ON: DE90009509
Resource Relation:
Conference: 1990 AT T conference on electronic testing, Princeton, NJ (USA), -10 May 1990
Country of Publication:
United States
Language:
English

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36 MATERIALS SCIENCE
42 ENGINEERING
99 GENERAL AND MISCELLANEOUS//MATHEMATICS, COMPUTING, AND INFORMATION SCIENCE
INTEGRATED CIRCUITS
SIMULATION
SEMICONDUCTOR MATERIALS
DEFECTS
TESTING
AUTOMATION
ALGORITHMS
COMPARATIVE EVALUATIONS
ECONOMICS
MANUFACTURING
MATHEMATICAL LOGIC
MEASURING METHODS
OPERATION
RESPONSE FUNCTIONS
ELECTRONIC CIRCUITS
FUNCTIONS
MATERIALS
MICROELECTRONIC CIRCUITS
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426000 - Engineering- Components
Electron Devices & Circuits- (1990-)
990200 - Mathematics & Computers