Article

Enhancing data cache reliability by the addition of a small fully-associative replication cache

Author:

Wei ZhangAuthors Info & Claims

ICS '04: Proceedings of the 18th annual international conference on Supercomputing

Pages 12 - 19

https://doi.org/10.1145/1006209.1006212

Published: 26 June 2004 Publication History

Abstract

Soft error conscious cache design is a necessity for reliable computing. ECC or parity-based integrity checking technique in use today either compromises performance for reliability or vice versa, and the N modular redundancy (NMR) scheme is too costly for microprocessors and applications with stringent cost constraint. This paper proposes a novel and cost-effective solution to enhance data reliability with minimum impact on performance. The idea is to add a small fully-associative cache to store the replica(s) of every write to the L1 data cache. The replicas can be used to detect and correct soft errors. The replication cache can also be used to increase performance by reducing the L1 data cache miss rate. Our experiments show that more than 97% read hits of the L1 data cache can find replicas available in a replication cache of 8 blocks.

References

[1]

J. Karlsson, P. Ledan, P. Dahlgren, and R. Johansson. Using heavy-ion radiation to validate fault handling mechanisms. IEEE Micro, 14(1):8--23, February 1994.

Digital Library

[2]

J. Sosnowski. Transient fault tolerance in digital systems. IEEE Micro, 14(1):24--35, February 1994.

Digital Library

[3]

S. Kim and A. Somani. Area efficient architectures for information integrity checking in cache memories. Proceedings of International Symposium on Computer Architecture, May 1999, pp. 246--256.

Digital Library

[4]

P.Shivakumar, M. Kistler, S. Keckler, D. Burger and L. Alvisi. Modeling the effect of technology trends on soft error rate of combinational logic. Proceedings of the International Conference on Dependable Systems and Networks, June, 2002.

Digital Library

[5]

J. Ray, J. C Hoe and B. Falsafi. Dual use of superscalar datapath for transient-fault detection and recovery. MICRO, December, 2001.

Digital Library

[6]

P. Sweazey. SRAM organization, control, and speed, and their effect on cache memory design. Midcon/87, pages 434--437, Septembe, 1987.

[7]

H. Imai. Essentials of error-control coding techniques. Academic Press, San Diego, CA, 1990.

Digital Library

[8]

C. L. Chen and M. Y Hsiao. Error-correcting codes for semiconductor memory applications: a state of the art review. In Reliable Computer Systems - Design and Evaluation, pages 771--786, Digital Press, 2nd edition, 1992.

[9]

W. Zhang, S. Gurumurthi, M. kandemir and A. Sivasubramaniam. ICR: in-cache replication for enhancing data cache reliability. Proceedings of DSN, 2003.

[10]

M. Hamada and E. Fujiwara. A class of error control codes for byte organized memory system-SbEC-(Sb+S)ED codes. IEEE Trans. on Computers, 46(1):105--110, January 1997.

Digital Library

[11]

S. Park and B. Bose. Burst asymmetric/unidirectional error correcting/detecting codes. Proceeding of International Symposium on Fault-Tolerant Computing, pages 273--280, June 1990.

[12]

E. Rotenburg. AR-SMT: A microarchitectural approach to fault tolerance in microprocessors. In Proceedings of the 29th International Symposium on Fault-Tolerant Computing Systems, June 1999.

Digital Library

[13]

S. K. Reinhardt and S. S. Mukherjee. Transient fault detection via simultaneous multithreading. In Proceedings of the 27th International Symposium on Computer Architecture, June 2000.

Digital Library

[14]

T. Austin. DIVA: a reliable substrate for deep submicron microarchitecture design. In Proceedings of the 32th International Symposium on Microarchitecture, Nov 1999.

Digital Library

[15]

V. Degalahal, N. Vijaykrishnan, M. J Irwin, "Analyzing Soft Errors in Leakage Optimized SRAM Design", In the Proceedings of VLSI Design conference January 2003.

Digital Library

[16]

Understanding Soft and Firm Errors in Semiconductor Devices. Actel Whitepaper, 2002.

[17]

A.J. Smith. Cache memories. Computing Surveys, Vol. 14, No. 3, September 1982.

Digital Library

[18]

J. Hennessy and D. Patterson. Computer architecture: a quantitative approach. Morgan Kaufmann Publishers, 1995.

Digital Library

[19]

N. P. Jouppi. Improving direct-mapped cache performance by the audition of a small fully-associative cache and prefetch buffers. In Proceedings of the 17th Annual International Symposium on Computer Architecture, May, 1990.

Digital Library

[20]

http://www.simplescalar.com.

[21]

http://www.spec.org.

[22]

AMD Athlon 64 FX Processor Data Sheet.

[23]

P. Shivakumar and N. Jouppi. CACTI 3.0: An integrated cache timing, power and area model. WRL Research Report 2001.

[24]

J. Kin, M. Gupta and W.H. Mangione-Smith. The filter cache: an energy efficient memory structure. In Proceedings of International Symposium on Microarchitecture, pages 184--193, 1997.

Digital Library

Cited By

Zhang YJung C(2022)Featherweight Soft Error Resilience for GPUs2022 55th IEEE/ACM International Symposium on Microarchitecture (MICRO)10.1109/MICRO56248.2022.00030(245-262)Online publication date: Oct-2022
https://doi.org/10.1109/MICRO56248.2022.00030
Sorin DSorin D(2022)Error DetectionFault Tolerant Computer Architecture10.1007/978-3-031-01723-0_2(19-59)Online publication date: 5-Mar-2022
https://doi.org/10.1007/978-3-031-01723-0_2
Choudhury ASikdar B(2019)Soft Error Resilience in Chip Multiprocessor Cache using a Markov Model Based Re-usability Predictor2019 IEEE 37th International Conference on Computer Design (ICCD)10.1109/ICCD46524.2019.00072(468-476)Online publication date: Nov-2019
https://doi.org/10.1109/ICCD46524.2019.00072
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Index Terms

Enhancing data cache reliability by the addition of a small fully-associative replication cache
1. Hardware
  1. Integrated circuits
    1. Semiconductor memory
      1. Dynamic memory

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cover image ACM Conferences

ICS '04: Proceedings of the 18th annual international conference on Supercomputing

June 2004

360 pages

ISBN:1581138393

DOI:10.1145/1006209

General Chair:
Paul Feautrier
LIP, ENS Lyon
,
Program Chairs:
James Goodman
University of Auckland
,
André Seznec
IRISA, INRIA

Copyright © 2004 ACM.

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Published: 26 June 2004

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ICS04: International Conference on Supercomputing 2004

June 26 - July 1, 2004

Malo, France

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Overall Acceptance Rate 629 of 2,180 submissions, 29%

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Cited By

Zhang YJung C(2022)Featherweight Soft Error Resilience for GPUs2022 55th IEEE/ACM International Symposium on Microarchitecture (MICRO)10.1109/MICRO56248.2022.00030(245-262)Online publication date: Oct-2022
https://doi.org/10.1109/MICRO56248.2022.00030
Sorin DSorin D(2022)Error DetectionFault Tolerant Computer Architecture10.1007/978-3-031-01723-0_2(19-59)Online publication date: 5-Mar-2022
https://doi.org/10.1007/978-3-031-01723-0_2
Choudhury ASikdar B(2019)Soft Error Resilience in Chip Multiprocessor Cache using a Markov Model Based Re-usability Predictor2019 IEEE 37th International Conference on Computer Design (ICCD)10.1109/ICCD46524.2019.00072(468-476)Online publication date: Nov-2019
https://doi.org/10.1109/ICCD46524.2019.00072
Kim GKim JKim C(2019)Dynamic Selective Warp Scheduling for GPUs Using L1 Data Cache Locality Information10.1007/978-981-13-5907-1_24(230-239)Online publication date: 8-Feb-2019
https://doi.org/10.1007/978-981-13-5907-1_24
Bathen LDutt N(2014)SPMCloudACM Transactions on Design Automation of Electronic Systems10.1145/261175519:3(1-45)Online publication date: 23-Jun-2014
https://dl.acm.org/doi/10.1145/2611755
Bathen LDutt N(2014)Embedded RAIDs-on-chip for bus-based chip-multiprocessorsACM Transactions on Embedded Computing Systems10.1145/253331613:4(1-36)Online publication date: 10-Mar-2014
https://dl.acm.org/doi/10.1145/2533316
Parekh DChaudhary SShyamasundar RShastri LJanakiram DPadmanabhuni S(2013)Durable data storage in distributed non persistent caching environmentProceedings of the 6th ACM India Computing Convention10.1145/2522548.2523128(1-7)Online publication date: 22-Aug-2013
https://dl.acm.org/doi/10.1145/2522548.2523128
Chen LCao YZhang Z(2013)Free ECC: An efficient error protection for compressed last-level caches2013 IEEE 31st International Conference on Computer Design (ICCD)10.1109/ICCD.2013.6657054(278-285)Online publication date: Oct-2013
https://doi.org/10.1109/ICCD.2013.6657054
Wang SHu JZiavras S(2012)Replicating tag entries for reliability enhancement in cache tag arraysIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2011.211146920:4(643-654)Online publication date: 1-Apr-2012
https://dl.acm.org/doi/10.1109/TVLSI.2011.2111469
Bathen LDutt N(2012)Software Controlled Memories for Scalable Many-Core ArchitecturesProceedings of the 2012 IEEE International Conference on Embedded and Real-Time Computing Systems and Applications10.1109/RTCSA.2012.60(1-10)Online publication date: 19-Aug-2012
https://dl.acm.org/doi/10.1109/RTCSA.2012.60
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