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Experimental measurement of a novel power gating structure with intermediate power saving mode

Published: 09 August 2004 Publication History

Abstract

A novel power gating structure is proposed for low-power, high-performance VLSI. This power gating structure supports an intermediate power saving mode as well as a traditional power cut-off mode. To evaluate our power gating structure, we design and fabricate three different macros in 0.13 um CMOS bulk technology. Our measurement results show that the additional intermediate power-mode allows us to cover various power-performance trade-off regimes, compared to conventional power gating structures.

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      cover image ACM Conferences
      ISLPED '04: Proceedings of the 2004 international symposium on Low power electronics and design
      August 2004
      414 pages
      ISBN:1581139292
      DOI:10.1145/1013235
      Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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      Published: 09 August 2004

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      Author Tags

      1. clock gating
      2. ground bounce
      3. inductive noise
      4. power gating
      5. system-on-a-chip (SOC) design
      6. wake-up latency

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      ISLPED04
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      ISLPED04: International Symposium on Low Power Electronics and Design
      August 9 - 11, 2004
      California, Newport Beach, USA

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      • (2023)Performance of a Low-Power 6T-SRAM Cell for Energy-Efficient Leakage Reduction Using DTMOS TechniqueProceedings of Fourth International Conference on Communication, Computing and Electronics Systems10.1007/978-981-19-7753-4_59(769-785)Online publication date: 15-Mar-2023
      • (2021)ICAP: Designing Inrush Current Aware Power Gating Switch for GPGPU2021 IEEE International Conference on Networking, Architecture and Storage (NAS)10.1109/NAS51552.2021.9605434(1-8)Online publication date: Oct-2021
      • (2021)Optimum sizing of the sleep transistor in MTCMOS technologyAEU - International Journal of Electronics and Communications10.1016/j.aeue.2021.153882138(153882)Online publication date: Aug-2021
      • (2019)A Current-Mode Delay-based Hysteretic Buck Regulator with Enhanced Efficiency at Ultra-light loads for Low-Power MicrocontrollersIEEE Transactions on Power Electronics10.1109/TPEL.2019.2913151(1-1)Online publication date: 2019
      • (2019)An Energy-Efficient Graphics Processor in 14-nm Tri-Gate CMOS Featuring Integrated Voltage Regulators for Fine-Grain DVFS, Retentive Sleep, and ${V}_{\text{MIN}}$ OptimizationIEEE Journal of Solid-State Circuits10.1109/JSSC.2018.287509754:1(144-157)Online publication date: Jan-2019
      • (2019)Reusing Leakage Current for Improved Energy Efficiency of Multi-Voltage Systems2019 IEEE International Symposium on Circuits and Systems (ISCAS)10.1109/ISCAS.2019.8702425(1-5)Online publication date: May-2019
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      • (2017)Technologies for Realizing Normally-Off ComputingNormally-Off Computing10.1007/978-4-431-56505-5_5(65-101)Online publication date: 21-Jan-2017
      • (2016)A Survey on Power Gating Techniques in Low Power VLSI DesignInformation Systems Design and Intelligent Applications10.1007/978-81-322-2757-1_30(297-307)Online publication date: 4-Feb-2016
      • (2014)Techniques: Putting the Silicon to WorkThe Art of Software Thermal Management for Embedded Systems10.1007/978-1-4939-0298-9_4(79-93)Online publication date: 4-Jan-2014
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