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Constant-load energy recovery memory for efficient high-speed operation

Published:09 August 2004Publication History

ABSTRACT

This paper proposes a constant-load SRAM design for highly efficient recovery of bit-line energy with a resonant power-clock supply. For each bit-line pair, the proposed SRAM includes a dummy bit-line of sufficient capacitance to ensure that the memory array presents a constant capacitive load to the power-clock, regardless of data or operation. Using a single-phase power-clock waveform, read and write operations are performed with single-cycle latency. The efficiency of the proposed SRAM has been assessed through simulations of 128x256 arrays with 0.25µm process parameters and a 42/58 write/non-write access pattern. Assuming lossless power-clock generation, the proposed SRAM dissipates 37% less power than its conventional counterpart at 400MHz/2.5V. When the overhead of power-clock generation is included, the proposed SRAM dissipates at least 27% less power than conventional SRAM.

References

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    • Published in

      cover image ACM Conferences
      ISLPED '04: Proceedings of the 2004 international symposium on Low power electronics and design
      August 2004
      414 pages
      ISBN:1581139292
      DOI:10.1145/1013235

      Copyright © 2004 ACM

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      Association for Computing Machinery

      New York, NY, United States

      Publication History

      • Published: 9 August 2004

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