ABSTRACT
This paper proposes a constant-load SRAM design for highly efficient recovery of bit-line energy with a resonant power-clock supply. For each bit-line pair, the proposed SRAM includes a dummy bit-line of sufficient capacitance to ensure that the memory array presents a constant capacitive load to the power-clock, regardless of data or operation. Using a single-phase power-clock waveform, read and write operations are performed with single-cycle latency. The efficiency of the proposed SRAM has been assessed through simulations of 128x256 arrays with 0.25µm process parameters and a 42/58 write/non-write access pattern. Assuming lossless power-clock generation, the proposed SRAM dissipates 37% less power than its conventional counterpart at 400MHz/2.5V. When the overhead of power-clock generation is included, the proposed SRAM dissipates at least 27% less power than conventional SRAM.
- D. Somasekhar, Y. Ye, and K. Roy, "An energy recovery static RAM memory core," in IEEE Symposium on Low Power Electronics. IEEE, 1995, pp. 62--63.Google Scholar
- Y. Moon and D.K. Jeong, "A 32 x 32-b adiabatic register file with supply clock generator," IEEE Journal of Solid-State Circuits, vol. 33, no. 5, pp. 696--701, May 1998.Google ScholarCross Ref
- S. Avery and M. Jabri, "A three-port adiabatic register file suitable for embedded applications," in International Symposium on Low Power Electronics and Design. IEEE, 1998, pp. 288--292. Google ScholarDigital Library
- J.H. Kwon, J. Lim, and S.I. Chae, "A three-port nRERL register file for ultra-low-energy applications," in International Symposium on Low Power Electronics and Design. IEEE, 2000, pp. 161--166. Google ScholarDigital Library
- K.W. Ng and K.T. Lau, "A novel adiabatic register file design," Journal of Circuits, Systems, and Computers, vol. 10, no. 1, pp. 67--76, 2000.Google ScholarCross Ref
- N. Tzartzanis, W.C. Athas, and L. Svensson, "A low-power SRAM with resonantly powered data, address, word, and bit lines," in European Solid-State Circuits Conference, 2000, pp. 336--339.Google Scholar
- J. Kim, C.H. Ziesler, and M.C. Papaefthymiou, "Energy recovering static memory," in International Symposium on Low Power Electronics and Design. IEEE, 2002, pp. 92--97. Google ScholarDigital Library
- J. Kim and C.H. Ziesler, "Fixed-load energy recovery memory for low power," in International Symposium on Very Large Scale Integration (VLSI) Systems, February 2004, pp. 145--150.Google Scholar
- C.H. Ziesler, J. Kim, and M.C. Papaefthymiou, "Energy recovering ASIC design," in International Symposium on Very Large Scale Integration (VLSI) Systems, April 2003, pp. 133--138. Google ScholarDigital Library
Index Terms
Constant-load energy recovery memory for efficient high-speed operation
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