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Efficient digit-serial normal basis multipliers over binary extension fields

Published: 01 August 2004 Publication History

Abstract

In this article, two digit-serial architectures for normal basis multipliers over (GF(2m)) are presented. These two structures have the same gate count and gate delay. We also consider two special cases of optimal normal bases for the two digit-serial architectures. A straightforward implementation leaves gate redundancy in both of them. An algorithm that can considerably reduce the redundancy is also developed. The proposed architectures are compared with the existing ones in terms of gate and time complexities.

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    cover image ACM Transactions on Embedded Computing Systems
    ACM Transactions on Embedded Computing Systems  Volume 3, Issue 3
    August 2004
    202 pages
    ISSN:1539-9087
    EISSN:1558-3465
    DOI:10.1145/1015047
    Issue’s Table of Contents
    Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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    Published: 01 August 2004
    Published in TECS Volume 3, Issue 3

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    Author Tags

    1. Digit-serial multiplier
    2. finite field
    3. normal basis
    4. security

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