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Towards fault-tolerant cryptographic computations over finite fields

Published: 01 August 2004 Publication History

Abstract

Cryptographic schemes, such as authentication, confidentiality, and integrity, rely on computations in very large finite fields, whose hardware realization may require millions of logic gates. In a straightforward design, even a single fault in such a complex circuit is likely to yield an incorrect result and may be exploited by an attacker to break the cryptosystem. In this regard, we consider computing over finite fields in presence of certain faults in multiplier circuits. Our work reported here deals with errors caused by such faults in polynomial basis multipliers over finite fields of characteristic two and presents a scheme to correct single errors. Towards this, pertinent theoretical results are derived, and both bit-parallel and bit-serial fault tolerant multipliers are proposed.

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Cited By

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  • (2014)On Selection of Modulus of Quadratic Codes for the Protection of Cryptographic Operations against Fault AttacksIEEE Transactions on Computers10.1109/TC.2012.23663:5(1182-1196)Online publication date: 1-May-2014
  • (2013)Power-Efficient Fault-Tolerant Finite Field MultiplierEnergy-Efficient Fault-Tolerant Systems10.1007/978-1-4614-4193-9_8(269-306)Online publication date: 12-Jul-2013
  • (2011)On Protecting Cryptographic Applications Against Fault Attacks Using Residue CodesProceedings of the 2011 Workshop on Fault Diagnosis and Tolerance in Cryptography10.1109/FDTC.2011.14(69-79)Online publication date: 29-Sep-2011
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        cover image ACM Transactions on Embedded Computing Systems
        ACM Transactions on Embedded Computing Systems  Volume 3, Issue 3
        August 2004
        202 pages
        ISSN:1539-9087
        EISSN:1558-3465
        DOI:10.1145/1015047
        Issue’s Table of Contents
        Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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        Published: 01 August 2004
        Published in TECS Volume 3, Issue 3

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        Author Tags

        1. Error correction
        2. fault-tolerant computing
        3. finite fields
        4. polynomial basis multiplier
        5. security

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        View all
        • (2014)On Selection of Modulus of Quadratic Codes for the Protection of Cryptographic Operations against Fault AttacksIEEE Transactions on Computers10.1109/TC.2012.23663:5(1182-1196)Online publication date: 1-May-2014
        • (2013)Power-Efficient Fault-Tolerant Finite Field MultiplierEnergy-Efficient Fault-Tolerant Systems10.1007/978-1-4614-4193-9_8(269-306)Online publication date: 12-Jul-2013
        • (2011)On Protecting Cryptographic Applications Against Fault Attacks Using Residue CodesProceedings of the 2011 Workshop on Fault Diagnosis and Tolerance in Cryptography10.1109/FDTC.2011.14(69-79)Online publication date: 29-Sep-2011
        • (2011)A dynamically error correctable bit parallel Montgomery multiplier over binary extension fields2011 20th European Conference on Circuit Theory and Design (ECCTD)10.1109/ECCTD.2011.6043614(600-603)Online publication date: Aug-2011
        • (2010)Design and implementation of robust embedded processor for cryptographic applicationsProceedings of the 3rd international conference on Security of information and networks10.1145/1854099.1854137(178-185)Online publication date: 7-Sep-2010
        • (2010)On the design of different concurrent EDC schemes for S-Box and GF(p)2010 11th International Symposium on Quality Electronic Design (ISQED)10.1109/ISQED.2010.5450467(211-218)Online publication date: Mar-2010
        • (2010)A Hybrid Scheme for Concurrent Error Detection of Multiplication over Finite FieldsProceedings of the 2010 IEEE 25th International Symposium on Defect and Fault Tolerance in VLSI Systems10.1109/DFT.2010.54(399-407)Online publication date: 6-Oct-2010
        • (2009)Concurrent Error Detection in Finite-Field Arithmetic Operations Using Pipelined and Systolic ArchitecturesIEEE Transactions on Computers10.1109/TC.2009.6258:11(1553-1567)Online publication date: 1-Nov-2009
        • (2009)On the synthesis of bit-parallel Galois field multipliers with on-line SEC and DEDInternational Journal of Electronics10.1080/0020721090316834896:11(1161-1173)Online publication date: Nov-2009
        • (2008)Sequential Circuit Design for Embedded Cryptographic Applications Resilient to Adversarial FaultsIEEE Transactions on Computers10.1109/TC.2007.7078457:1(126-138)Online publication date: 1-Jan-2008
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