Article

Reducing test time with processor reuse in network-on-chip based systems

Authors:

Alexandre M. Amory,

Marcelo Lubaszewski,

Fernando G. MoraesAuthors Info & Claims

SBCCI '04: Proceedings of the 17th symposium on Integrated circuits and system design

Pages 111 - 116

https://doi.org/10.1145/1016568.1016602

Published: 04 September 2004 Publication History

Abstract

This paper proposes a test planning method capable of reusing available processors as test sources and sinks, and the on-chip network as the access mechanism for the test of cores embedded into a system on chip. The resulting test time of the system is evaluated considering the number of reused processors, the number of external interfaces, and power dissipation. Experimental results for a set of industrial examples based on the ITC'02 benchmarks show that the cooperative use of both the on-chip network and the embedded processors can increase the test parallelism and reduce the test time.

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Cited By

Hu CLi ZXu CZhu AJia M(2017)Test scheduling with bandwidth division multiplexed for network-on-chip using refined quantum-inspired evolutionary algorithmJournal of Computational Methods in Sciences and Engineering10.3233/JCM-16070216:4(927-941)Online publication date: 17-Jan-2017
https://doi.org/10.3233/JCM-160702
Lee S(2013)Reusing existing resources for testing a multi-processor system-on-chipInternational Journal of Electronics10.1080/00207217.2012.713011100:3(355-370)Online publication date: Mar-2013
https://doi.org/10.1080/00207217.2012.713011
Salamy HHarmanani H(2012)An effective solution to thermal-aware test scheduling on network-on-chip using multiple clock rates2012 IEEE 55th International Midwest Symposium on Circuits and Systems (MWSCAS)10.1109/MWSCAS.2012.6292074(530-533)Online publication date: Aug-2012
https://doi.org/10.1109/MWSCAS.2012.6292074
Show More Cited By

Index Terms

Reducing test time with processor reuse in network-on-chip based systems
1. Hardware
  1. Hardware test
  2. Robustness

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Published In

cover image ACM Conferences

SBCCI '04: Proceedings of the 17th symposium on Integrated circuits and system design

September 2004

296 pages

ISBN:1581139470

DOI:10.1145/1016568

General Chair:
Edna Natividade da Silva Barros
Federal University of Pernambuco, Brazil
,
Program Chairs:
Flàvio Rech Wagner
Federal University of Rio Grande do Sul, Brazil
,
Luigi Carro
Federal University of Rio Grande do Sul, Brazil
,
Franz Josef Rammig
University of Paderborn, Germany

Copyright © 2004 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Publication History

Published: 04 September 2004

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SBCCI04

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SBCCI04: 17th Symposium on Integrated Circuits and System Design

September 7 - 11, 2004

Pernambuco, Brazil

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Overall Acceptance Rate 133 of 347 submissions, 38%

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Cited By

Hu CLi ZXu CZhu AJia M(2017)Test scheduling with bandwidth division multiplexed for network-on-chip using refined quantum-inspired evolutionary algorithmJournal of Computational Methods in Sciences and Engineering10.3233/JCM-16070216:4(927-941)Online publication date: 17-Jan-2017
https://doi.org/10.3233/JCM-160702
Lee S(2013)Reusing existing resources for testing a multi-processor system-on-chipInternational Journal of Electronics10.1080/00207217.2012.713011100:3(355-370)Online publication date: Mar-2013
https://doi.org/10.1080/00207217.2012.713011
Salamy HHarmanani H(2012)An effective solution to thermal-aware test scheduling on network-on-chip using multiple clock rates2012 IEEE 55th International Midwest Symposium on Circuits and Systems (MWSCAS)10.1109/MWSCAS.2012.6292074(530-533)Online publication date: Aug-2012
https://doi.org/10.1109/MWSCAS.2012.6292074
Salamy HHarmanani H(2011)An optimal formulation for test scheduling network-on-chip using multiple clock rates2011 24th Canadian Conference on Electrical and Computer Engineering(CCECE)10.1109/CCECE.2011.6030441(000215-000218)Online publication date: May-2011
https://doi.org/10.1109/CCECE.2011.6030441
Berg ARen PMarinissen EGaydadjiev GGoossens K(2010)Bandwidth Analysis of Functional Interconnects Used as Test Access MechanismJournal of Electronic Testing: Theory and Applications10.1007/s10836-010-5163-x26:4(453-464)Online publication date: 1-Aug-2010
https://dl.acm.org/doi/10.1007/s10836-010-5163-x
Berg ARen PMarinissen EGaydadjiev GGoossens K(2008)Bandwidth Analysis for Reusing Functional Interconnect as Test Access MechanismProceedings of the 2008 13th European Test Symposium10.1109/ETS.2008.34(21-26)Online publication date: 25-May-2008
https://dl.acm.org/doi/10.1109/ETS.2008.34
Hussin FYoneda TFujiwara H(2008)NoC-Compatible Wrapper Design and Optimization under Channel-Bandwidth and Test-Time ConstraintsIEICE - Transactions on Information and Systems10.1093/ietisy/e91-d.7.2008E91-D:7(2008-2017)Online publication date: 1-Jul-2008
https://dl.acm.org/doi/10.1093/ietisy/e91-d.7.2008
Hussin FYoneda TFujiwara H(2008)On NoC Bandwidth Sharing for the Optimization of Area Cost and Test Application TimeIEICE - Transactions on Information and Systems10.1093/ietisy/e91-d.7.1999E91-D:7(1999-2007)Online publication date: 1-Jul-2008
https://dl.acm.org/doi/10.1093/ietisy/e91-d.7.1999
Hussin FYoneda TFujiwara H(2007)Optimization of NoC Wrapper Design under Bandwidth and Test Time ConstraintsProceedings of the 12th IEEE European Test Symposium10.1109/ETS.2007.30(35-42)Online publication date: 20-May-2007
https://dl.acm.org/doi/10.1109/ETS.2007.30
Hussin FYoneda TFujiwara H(2007)Area Overhead and Test Time Co-Optimization through NoC Bandwidth Sharing16th Asian Test Symposium (ATS 2007)10.1109/ATS.2007.22(459-462)Online publication date: Oct-2007
https://doi.org/10.1109/ATS.2007.22
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