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Accurate capture of timing parameters in inductively-coupled on-chip interconnects

Published: 04 September 2004 Publication History

Abstract

With continuously increasing on-chip frequencies and shortening signal rise time, inductance effects pose sever difficulties on efficient timing analysis. This work analyses the effects on different timing parameters of the inductive coupling in long and intermediate high-frequency on-chip interconnects. We show that crosstalk, noise, signal integrity, signal rise and fall times, all depend on the data toggling pattern. Moreover, the conclusion is drawn that the worst and best case switching patterns are not necessarily similar for capacitively coupled dominant and for mainly inductively coupled lines.

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  • (2024)A hybrid interface design based on chip edge connection and inductively coupling connection for 3D stacked chipsIEICE Electronics Express10.1587/elex.21.2024057721:24(20240577-20240577)Online publication date: 25-Dec-2024

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    cover image ACM Conferences
    SBCCI '04: Proceedings of the 17th symposium on Integrated circuits and system design
    September 2004
    296 pages
    ISBN:1581139470
    DOI:10.1145/1016568
    Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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    Publication History

    Published: 04 September 2004

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    Author Tags

    1. crosstalk
    2. inductive coupling
    3. interconnect models
    4. on-chip interconnects
    5. signal delay

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    • (2024)A hybrid interface design based on chip edge connection and inductively coupling connection for 3D stacked chipsIEICE Electronics Express10.1587/elex.21.2024057721:24(20240577-20240577)Online publication date: 25-Dec-2024

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