Static next sub-bank prediction for drowsy instruction cache

As feature sizes shrink, leakage energy reduction has become increasingly important, especially for cache memories. Recent research in drowsy instruction cache shows that the leakage energy of the instruction cache can be significantly reduced with little performance degradation by exploiting the instruction spatial locality at the cache sub-bank level[5]. The performance penalty due to the sub-bank wake-up latency is dramatically reduced by using a prediction buffer to pre-activate the next sub-bank at runtime. However, consulting the prediction buffer at every cache access consumes non-trivial dynamical energy, which can compromise the overall energy savings substantially. This paper proposes a static approach to capture the sub-bank transition behavior at link time and to pre-activate the instruction cache sub-bank at runtime according to the compiler-directed hints. We also propose a hybrid approach to exploit both the static and dynamic information for reducing the performance penalty further with little dynamic energy overhead. Our experiments reveal that the static approach is very successful in capturing the sub-bank transition behavior for reducing the performance penalty and it also reduces 38.2% more leakage energy than the hardware-based approach, taking the dynamic energy overhead into account. Moreover, our results show that the hybrid approach is the best strategy for the drowsy instruction cache to balance leakage energy reduction and performance.